What precisely is the resynchronization drawback when using adc_ker_ck?

[Mr_M_from_G]

Hello,

I want to use ADC1 and 2 with close to maximum sampling frequency. Now I found on page 899 in RM0433 Rev5 a note that there will be a resynchronization between adc clk (using adc_ker_ck to achieve the highest possible clock) and AHB1 clk. I don't understand that precisely and want to ask for some clarification.

Assumed I want:

5 MSps which is 200 nsec per sample, provided by a timer

36 MHz adc_ker_ck which can be created eg by PLL2 => period is about 28 nsec

Does that mean, a sampling trigger coming from timer must wait till the next adc_ker_ck say rising edge arrives? That would be a jitter of up to 14%. If so, is there a way to create a 5MHz (or something in that range) timer signal that is sychronous with adc_ker_ck?

Is there a way to precisely create a desired sampling rate when using ADC in continuous conversion mode?

Thanks for any help

kind regards

Martin

[waclawek.jan]

I'd assume, in continuous conversion there's no waiting for trigger thus no jitter...?

JW

[Mr_M_from_G]

Hello Jan,

maybe you are right. I am just trying to check it but ran into other trouble, see my latest post. I'll come back here when I have news.

Thanks a lot

Martin

[Mr_M_from_G]

Hello,

I promised to come back with results.

I managed to get ADC1 and 2 running with 12 bit resolution at 4.5 MSps. I generate adc_ker_ck with PLL2 and run ADC in continuous mode.

It is pretty hard to check sample clock jitter because I have no direct clock output. So I fed ADC with a ramp signal and compared one ramp segment with a straight line. The difference is in the range of DC noise. So for the first hit it looks good.

Martin

[waclawek.jan]

Thanks, Martin, for the info.

Jan

[Piranha]

Looking at RM0433 24.3.3 offered options:

1. There should not be jitter when ADC clock is driven from the same source and is exact multiple of AHB clock.
2. There will not be resynchronizations and therefore no jitter when ADC clock is derived directly from AHB clock.