What is written to the USART_BRR register?

[MMust.5]

What is this value that is written to the USART_BRR register?

What is it for?

I don’t understand why the calculation is done using the formula: fclock / (the divisor, in my formula it is 5 * baudrate)For example, here is an example calculation:

I made the numbers much smaller to simplify the example.

fclock / (divisor, in my formula it is 5*baudrate)

fclock ==Clock frequency==30 Hertz.

Desired baudrate==2

Divisor == 5

30 fclock / 2 baud * 5 divisor==3 this number is written to the USART_BRR register.

3 what is this number?

What is it for?

BRR== Baud Rate Register. But 3 is not the baudrate I needed. I have 2 desired baudrate.

Or does it not matter what my desired data rate is?

Why would I then enter the desired baud rate if that's the case?

Does this formula calculate the speed that will be applied, and not the speed that I need?

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Maybe this will be useful: Shown in the picture

If a marker is set every 3 bits at a clock frequency of 30 Hertz, based on these markers, we get a speed of 10 baud.

But I needed a speed of 2 baud, this formula: fclock / (divisor, in my formula it is 5 * baudrate) does not produce this calculation.

[Tesla DeLorean]

No idea what you're describing

For 16x Oversampling Mode

BRR = APBxClock / Baud

Say USART1, on APB2, with a clock of 24 MHz

24,000,000 / 115,200 = 208.3333 -> 208

[MMust.5]

USARTDIV=fclock / (16*baud)

USARTDIV=24000000/(16*115200)==13

And what is this number 13?

In this case, the USART_BRR register will be written to the number 13 0

HEX:D0

Decimal: 208

What is this number 208? I do not understand. 

This number is similar to the number of samples for each bit at the specified baud rate of 115200

[MMust.5]

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[gbm]

That's an old problem with STM32 Reference Manuals. Just forget this "division by 16" and "fractional part" and everything becomes simple. For 16x oversampling (default), the value in BRR should be the properly rounded result of dividing the UART input clock by the baud rate. That's it. No "fractions", no "div by 16".

It is almost the same in 8x oversampling mode. The only difference is bit 3 of BRR is not used and the result of division is written to bits 15..4 and 2..0.

Also, see this link:

https://community.st.com/s/question/0D53W00001UxfdySAB/errors-in-uart-baud-rate-sections-of-reference-manuals

[MMust.5]

24,000,000 / 115,200 = 208

Number 208 What is it?

It's not the baud rate.

The baud rate is 13 baud.

24000000/16*115200==13

[Tesla DeLorean]

>> Number 208 What is it? It's not the baud rate.

USART1->BRR = 208

Like I said BRR = APBxClock / Baud

The logic doesn't do math, it is a counter, acting as a divider. This is relatively simple to do with logic gates, and thus transistors. The UART doesn't have any code running inside it, it is a machine.

The 16x over-sampling matches well with the 4-bit fractional model

The BRR is NOT the baud rate

Baud Rate = APBxCLK / USARTx->BRR

Baud Rate =24,000,000 / 208

Baud Rate = 115384.62 ie 115200 +0.16%

BBR = 2500

24,000,000 / 2500

9600 baud

[gbm]

115200 is the baud rate; UART_CLOCK / BAUD _RATE (correctly rounded) is the value written to BRR register. BRR is a baud rate divisor register. That's it. Forget "mantissa" and "fraction". UART input clock divided by BRR content gives the baud rate.