What is the WDG_LS_D1 in STM32H7 MCUs?

In the previous ST products (mostly the STM32F and L series) I was able to disable the IWDG when code went into debug.

Unfortunately, in the H7 I can see the introduction of new mechanism controlled by bit WDGLSD1 in DBGMCU_APB4FZ1 register.

On the block diagram for the H7 MCUs I can see some correlation to this mechanism:

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but there is no much of a description how it works.

In previous products there was specific bit to freeze the IWDG, by setting the DBG_IWDG_STOP bit.

Is there anyone who can describe how freezing the watchdog works in the H7 series.

Best regards

Tomasz Zeman

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