Skip to main content
bivin mato
Associate III
May 3, 2020 1:12 PM UTC
Solved

What is the right sequence to enable under-drive mode in STM32F779NI ?

Hello,

I'm not able to enable MR under-drive mode in my STM32F779NI chip.

The exact problem is UDRDY is not getting set -> Line number 39 to 43.

Below is the code snippet. Any suggestion would be very helpful. Thanks in advance.

int main(void)
{
	/* Add your application code here */
	__IO uint32_t tmpreg;
 
	/* Enable clock for toggle LED */
	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);
	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);
 
	/* Enable clock for switch input (EXTI) */
	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
 
	/* Enable clock for SYSCFG that connects switch to EXTI */
	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);
	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);
 
	/* Enable clock for PWR module */
	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
 
	/* Configure toggle LED */
	GPIOI->MODER |= GPIO_MODER_MODER15_0;
	GPIOI->PUPDR |= GPIO_PUPDR_PUPDR15_0;
	GPIOI->OSPEEDR |= GPIO_OSPEEDR_OSPEEDR15;
	GPIOI->BSRR= GPIO_BSRR_BS15; // Reset
 
	/* Configure switch input */
	GPIOC->PUPDR = 0;
	GPIOC->MODER = 0;
	SYSCFG->EXTICR[3] = 0x20;
	EXTI->IMR = 0x2000;
	EXTI->EMR = 0;
	EXTI->RTSR = 0x2000;
 
	NVIC_SetPriority(EXTI15_10_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 2, 0));
	NVIC_EnableIRQ(EXTI15_10_IRQn);
 
	SET_BIT(PWR->CR1, PWR_CR1_MRUDS);
 
	PWR->CR1 |= PWR_CR1_UDEN;
 
	while( ! ((READ_BIT(PWR->CSR1, PWR_CSR1_UDRDY)) == PWR_CSR1_UDRDY ) );
 
	/* Infinite loop */
	while (1)
	{
		/* Set SLEEPDEEP bit of Cortex System Control Register */
		SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
 
		/* Ensure that all instructions done before entering SLEEP mode */
		__DSB();
		__ISB();
 
		/* Request Wait For Interrupt */
		__WFI();
 
		/* Reset SLEEPDEEP bit of Cortex System Control Register */
		SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
	}
}

Regards,

Bivin

This topic has been closed for replies.
TDK
TDKBest answer
May 3, 2020 1:41 PM UTC

It looks like UDRDY bits get set only when the CPU enters stop mode. You can check for and clear them after it wakes back up.

0693W000000Wo6hQAC.png

"If you feel a post has answered your question, please click ""Accept as Solution""."

3 replies

TDK
TDKBest answer
May 3, 2020 1:41 PM UTC

It looks like UDRDY bits get set only when the CPU enters stop mode. You can check for and clear them after it wakes back up.

0693W000000Wo6hQAC.png

"If you feel a post has answered your question, please click ""Accept as Solution""."
bivin mato
Associate III
May 3, 2020 1:53 PM UTC

Sorry. I overlooked this information. Thanks a lot ! :)

Regards

Bivin