What is the relationship between SPI clock and compiler optimization on STM32L0 ?
Hi,
I'm working on a custom board where we integrated an STM32L010RB and I have verry weird behaviour :
I need to use SPI1 peripheral and the clock signal is working as expected only if I enable optimization on the compiler settings.
The MISO is OK.
In STM32Cube IDE the SPI_CLK signal is routed by default to PA5.
If I use the PA5 PIN for SPI_CLK, my clock signal works as expected with or without optimizations.
If I change to use PB3 (which is the pin I need to use on my design), I have a signal on clk only if I enable a compiler optimization (any of it). But in this case some of my GPIO are not working (i.e. I can't read the correct pin state for inputs and cannot drive my outputs)
I really don't understand what this means, the relation between optimization and the fact it works or not. In fact, I can understand that optimization could lead to a buggy behaviour because of interrupts, or something else, but how can it fix a bug on SPI and produce bugs on GPIOs ?
I don't want to use optimizations, so how to make my SPI work without optimizations ? I'm completely lost !
Thanks in advance for your help.
Bye.
