What is the relationship between adc clock and sample rate? [STM32H7]
I understand the sampling rate for 16-bit can be a maximum of 3.6Msps depending on the chip package, number of ADCs, oversampling, and interleaving or regular..
I'm doing a regular 3 channels 16-bit scan from a single ADC, no oversampling.
The app note says the maximum fadc clock is 50mhz, but CubeMx's clock configuration tool allows values higher than that... so does that mean one must set the sampling cycles to be AT LEAST greater than 41.7ns when connected to FAST channels, and AT LEAST greater than 150ns when connected to SLOW channels, otherwise the readings will be bad?
If so, is it possible to run the ADC such that it continuously scan/convert without the use of a timer or without having to start it after scan completion?
void test_adc(){
uint8_t buf[64];
int len = 1;
volatile float adcf;
memset(&s_pAlignedAdcBuffer[0], 0xff, sizeof(s_pAlignedAdcBuffer));
SCB_CleanDCache_by_Addr((uint32_t*)&s_pAlignedAdcBuffer[0], sizeof(s_pAlignedAdcBuffer));
while(1){
if (!isAdcWork){
isAdcWork = true;
SCB_InvalidateDCache_by_Addr((uint32_t*)&s_pAlignedAdcBuffer[0], sizeof(s_pAlignedAdcBuffer));
//HAL_ADCEx_MultiModeStart_DMA(&hadc1, (uint32_t*)&s_pAlignedAdcBuffer[0], 6);
dbg_res = HAL_ADC_Start_DMA(&hadc1,(uint32_t*)&s_pAlignedAdcBuffer[0], 6);
}
len = snprintf(buf, sizeof(buf), "%u %d\r\n", adcCounter, s_pAlignedAdcBuffer[0]);
HAL_UART_Transmit(&huart3, buf, len, HAL_MAX_DELAY);
HAL_Delay(1000);
}
