What is the maximum supported rate for SPI peripherals on stm32h503rbt6u chips in slave mode?

[taylor_quan]

I use spi1 as the slave to receive data, and if the speed of the spi master is set above 11M, the data received will be misaligned.I would like to know what is the maximum speed supported by the SPI peripheral on the stm32h503rbt6u chip in the slave mode?

[gbm]

And what exactly do you mean by "misaligned"?

My wild guess is: if by "misaligned" you mean missing/extra frames then it has nothing to do with hardware but rather depends on software - the software reaction time. It's generally hard to implement an intelligent (responding to commands) SPI slave with a microcontroller.

If it's a hardware thing and you see bits being "midaligned" then check the speed setting of all SPI lines on both sides. In particular check if master NSS output (usually software-controlled GPIO) is set to maximum speed.

[taylor_quan]

As shown in the above figure, when the speed set by the spi master exceeds 11M, the data sent by the slave appears to have lost bits

[AScha.3]

from ds :

 

so 120MHz max.   ; how long are the wires ? ground /shield ? damping resistors ?

 

[taylor_quan]

May I ask which document should I refer to for this image? I am using a DuPont cable, and the master and slave devices use the same ground

 

[AScha.3]

cpu data...

 

 

[waclawek.jan]

How does the physical connection look like? Can you show photos?

What are the logic levels at both sides?

Is NSS low all the time during transmission?

JW

[taylor_quan]

The physical connection is shown in the figure above.
The logic level is all 3.3v.
NSS has always been low, but it is not used in firmware

 

[waclawek.jan]

Read the article I linked to.

12MHz is not a trivial frequency.

JW