What is the internal clock CK_INT for the STM32H7 timers?

[eBirdman]

The STM32H743 datasheet says nothing about clocking the timers. Reference manual has a chapter dedicated to each timer's counter clocking. For each type of timer the only clock is so called "Internal Clock" CK_INT . What is it? Opened my project's CubeMX Clock Configuration and I don't find such label there. Trying to guess which clock could be used to run timers, I'd assume one of those: APB1 Timer clocks or APB2 timer clocks .

But again - which one is that mysterious CK_INT from the reference manual ? And is it one for all timers or are they using different clock sources?

Please help to understand this.

[waclawek.jan]

The RCC chapter describes the clocks to individual peripherals.

JW

[TDK]

Some timers are on APB1, and some are on APB2. And some timers such as LPTIM and HRTIM can select from a few different options.

[eBirdman]

Thank you Jan - this was a good pointer to find the answer. Although the way to find it in that chapter was also not straight forward. I expected to find something like a table showing what clock drives what peripheral. Nothing of the sort, even in the chapter 8.5.10 called "Peripheral allocation" there is no really specific peripheral allocation given. But I found it indirectly browsing through the description of all the RCC clock registers until I found the bit for TIM6 .

May be I just want too much asking for a direct answer in description or in a table for "which clock drives TIM6 timer" ?

Anyways, thank you for this hint.

Vlad.

[eBirdman]

To sum up for others searching to find internal clock driving a particular peripheral :

search through the chapters 8.7.x for the registers called RCC *** Clock Register until you find a bit in one of them matching your peripheral.

Example : register RCC_APB1LENR bit TIM6EN enables TIM6 timer.

[waclawek.jan]

That's one thing, clocks to individual peripherals are enabled in the respective RCC_APBxENR registers.

But how exactly clocks for *timers* are generated, is somewhat convoluted, it's not straightforwardly equal to the respective APB bus frequency. See System clock generation subchapter of RCC chapter, rcc_timx_ker_ck and rcc_timy_ker_ck (for timers on APB1 and APB2, respectively); observe the Core and bus clock generation figure and  Ratio between clock timer and pclk table, and then check the description of RCC_D2CFGR.DD2PPREx and RCC_CFGR.TIMPRE bits referenced there.

JW

[eBirdman]

Indeed, I also failed to see any use of the kernel clocking to gate RCC bus clocking. I am using CubeMX for clock generation. All I need is to know which clock bus is driving each peripheral. This allows to configure clock bus' prescaler, get proper bus output frequency (for ex. APB1 output), then configure Timer peripheral counter prescaler and ARR, and hence get proper output timing. So this "clock bus + kernel gating" staff is not even in the CubeMX picture. If CubeMX clocking configuration does not care about peripheral kernel gating, I conclude we developers don't need it...

Just for a comparison:

Very similar clock configuration tool for similar Cortex-M7 MCU by Microchip MPLAB Harmony shows rcc clocking for each named peripheral on the same clock configuration diagram. By checking the activation box for a given peripheral I allow it's clocking (activation) from the clearly shown clock bus. And I do configuration of that clock bus the same way as in CubeMX... easy, no research of a datasheet required .. (yet they have other much more severe problems than this)...

Vlad