What is the correct maximum FMC clock on a STM32F767 ?

[SylvainF]

Hi, I am currently working on a display driver board, with a STM32F767. And I would like to use the FMC with a SDRAM.

My problem is that the MCU is clocked at 216MHz, the SDRAM max clock is 133MHz, on the F767 documentation, it is written that the max FMC clock is 100MHz, but it is also written that the FMC clock is HCLK/2, so my question is : is it okay to run the FMC at 108MHz (HCLK/2), or do I have to clock my MCU at 200MHz to get the 100MHz clock for the FMC ?

Thank you, Sylvain.

[Pavel A.]

It looks like FMC has additional divisor for SDRAM.

Below is screenshot of my config for STM32F767 with LCD and display buffer in SDRAM.

[SylvainF]

Hi Paval, thanks for your answer,

Yes I am aware of this additionnal divisor but it would clock the FMC at 72MHz. So in that case, I would prefere to run the MCU at 200MHz to use HCLK/2 to clock the FMC at 100MHz :grinning_face_with_sweat:

Maybe it is possible to "overclock" the FMC :beaming_face_with_smiling_eyes:

Best regards

[Tesla DeLorean]

Likely comes down the the pin drivers, and getting signals off-chip

Generally I don't think SDRAM implementations with short/managed traces need the most aggressive slew-rate (speed) settings available.

I would expect 108 MHz could be hit with a clean design.

Lots of different trade-offs here derating has perhaps benefits of lower power and EMI.

You'd probably want to test/validate boards as built, and in consultation with a local FAE