Question
What is the architecture of the differential ADC in STM32H750?
Basic SAR ADC is depicted here:
STM32H750 showed it’s ADC block:
I want to know what is inside this block? Why it’s input signal should biased to 1.65+-10% strictly? But It’s sigle ended arrangement which is simply connect the negative pin to gnd have large common mode input from 0 to Vcc?