What does Data length and channel length mean both in Master and Slave mode?
Hi guys, been working on an I2S project for a while now and I am having such confusion on this bit registers "CHLEN" and "DATLEN".
In Master mode it seems like CHLEN determines the frequency of the SLCK by
2 * CHLEN length * FS and data length I have no idea what it does
and in slave no idea how they both work as the master will provide these signals now.
I had times where it works with CHLEN = 16bit and DATLENGTH = 16bit same with CHLEN = 32BIT And DATALENGTH = 32bit and I have no idea.
Would anyone please explain to me how these registers purpose and how should they set up?
