Weird triggering of SPI interruption on STM32H743

[Gpeti]

I'm facing a weird situation. I'm using SPI simplex receive-only mode on a Slave STM32H743. It has been working fine for a while. Until now I was enabling only the RXP interruption. The SPI1 interrupt was triggered as expected.

Now I enabled also EOTIE. No other modification. As soon as I enable the interruption I've got an interrupt on SPI1, even if the master is not communicating.

As you can see below the SPI1 interruption is asserted but there is not bit in common between registers SR and IER. The mapping of interrupt handler is correct in the vector table.

How is it possible that the interrupt is asserted ?

[berendi]

There is no 1:1 relationship between SR and IER. EOT interrupt can be triggered by multiple events, with TXC among them which is set.

[Gpeti]

You're right, I missed this point. However I am in receive only (simplex) slave mode, so the TxFIFO remains empty all the time. what am I supposed to do before enabling EOT event in reception, to avoid this flasg TXC to be set (or to clear it) ?

[berendi]

What should trigger the interrupt? A rising edge on NSS? You can configure an EXTI interrupt on the NSS pin, it works even when the pin is in alternate (or output) mode.

[Gpeti]

Well i thouht the EOT interrupt could be simply triggered (at slave receive only mode) when TSIZE bytes have been received.

[berendi]

TSERF maybe?