Weird PWM Timer3 master and PWM Timer1 slave behaviour

[Xxoyo.1]

Hello, I have a timer 3 master and timer 1 slave. When a button is pressed, master is activated as long as button is pressed, and then slave is triggered based on master's output signal (high / low) (gated slave control)

(

This is a continuation of my previous post here -> https://community.st.com/s/feed/0D53W00000uWUzeSAG

)

 Correct outputs (below)

 

 

Wrong outputs (below)

 

 

[TDK]

Is there a question? If you want the signal to be low, set it low during the falling edge interrupt.

[Xxoyo.1]

Hello, sorry for not clarifying the question at the start. My question is to why there is a portion of the slave output being held high when the master is already low level?

I would like to set it low during falling edge interrupt, but how to do that? Do i need to use forced timer output?

Thank your for your assistance!

[waclawek.jan]

Another option is to set the master's "active" time to integer multiple of the slave's period.

JW

[TDK]

The timer output channels run a on a very specified set of conditions. You need to ensure the CCRx value is what you what at the end of the period. As JW says, this can be done by ensuring the active duration is a multiple of the period.

Otherwise just set CCRx value to what you want (i.e. a value that produces a low output) at the end of the falling period.