Watchdog reset while changing CLock frequency

[jijo137]

Posted on October 14, 2015 at 16:13

I have configured my stm32f427 microcontroller,  Sysclk to run in a clock frequency of 60mhz(HSI and PLL). I have reduced it to 16mhz (Sysclk directly from HSI). While executing this code watchdog resets.

Below mentioned the code I have used to change the clock frequency.

RCC_HSICmd(ENABLE);

while(RCC_GetFlagStatus(RCC_FLAG_HSIRDY) == RESET);

RCC_HCLKConfig(RCC_SYSCLK_Div1); /* Configure HCLK same as SYSCLK */

RCC_PCLK1Config(RCC_HCLK_Div2);

RCC_PCLK2Config(RCC_HCLK_Div2);

Please help me in solving in this issue.

Thanks in Advance 

[Tesla DeLorean]

Posted on October 14, 2015 at 16:40

Wouldn't the obvious solution be to kick the watchdog in the while(1) loop?

Ask yourself how long the watchdog period is.

Ask yourself how long the HSI takes to start, check the specs, and verify in real life.

Consider if you need a timeout in the loop so it's not stuck in an infinite loop

[jpeacock]

Posted on October 14, 2015 at 19:33

You didn't specify IWDG or WWDG watchdog, or what the timer periods are.  For the IWDG, reset it periodically in the while loop, although an HSI startup should be short enough you can just hit the IDWG before switching frequency.

For the WWDG you need to wait until the window is long enough to complete the frequency change.  Just before or while in the HSI ready loop poll the WWDG counter and hit it once while it is inside the reset window.

Do you know which watchdog caused the reset?  The WWDG has an early warning interrupt you can use to make sure it won't time out; you can also reset the IWDG at the same time.  Not the best practice (the watchdogs should be independently reset at two different points) but it will get you running.

  Jack Peacock