watch Dog question

[ezrab]

Posted on October 20, 2010 at 11:29

hi

i saw that the slower watch dog i can make will reset after

 /* On Value line devices, Enable WWDG and set counter value to 127, WWDG timeout = ~1366 ×–s * 64 = 87.42 ms */

can i make it slower like 500msec?

thanks.

[Tesla DeLorean]

Posted on October 20, 2010 at 18:18

Use the Independent watchdog (IWDG) it has a 12-bit counter, and an 8-bit prescaler off the 40 KHz LSI. Max timeout is in the order of 26 seconds.

[ezrab]

Posted on October 21, 2010 at 08:24

hi.

i tried using the IWDG but for some reason it does not work when ever it needs to reset the CSTACK gets full and it does not start.

why?

#include ''stm32F10x.h''

#define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)

#define IWDG_Prescaler_32           ((uint8_t)0x03)

#define KR_KEY_Reload    ((uint16_t)0xAAAA)

#define KR_KEY_Enable    ((uint16_t)0xCCCC)

#define CSR_RMVF_Set              ((uint32_t)0x01000000)

void setsystemclock(void);

void uartfunction(void);

uint8_t TxBuffer[] = ''Buffer Send from USART3 to USARTz using Flags'';

uint8_t TxCounter = 0, RxCounter = 0;

int main(void)

{

char byte_temp=0;

    setsystemclock(); //set system clock to 24Mhz

    RCC->CSR |= CSR_RMVF_Set;

    //watchdog configuration

    IWDG->KR=IWDG_WriteAccess_Enable;//unlock WDG registers

    /* IWDG counter clock: 40KHz(LSI) / 32 = 1.25 KHz */

    IWDG->PR =IWDG_Prescaler_32;

    IWDG->RLR =349;//reload value

   IWDG->KR =KR_KEY_Reload;

    //IWDG->KR = KR_KEY_Enable;

    RCC->APB2ENR =RCC_APB2RSTR_IOPCRST | RCC_APB2RSTR_AFIORST;//port C clock and alternative clock enable. page 79

    RCC->APB1ENR =RCC_APB1ENR_USART3EN ;

      GPIOC->CRH=GPIO_CRH_MODE10 | GPIO_CRH_CNF10_1 |  GPIO_CRH_CNF11_0 ;//PC11 in input floating mode for RX. PC10 Alternative Output TX.

AFIO->MAPR=AFIO_MAPR_USART3_REMAP_0 ;//port remap as uart //PC10 TX PC11 RX

    USART3->CR1 =USART_CR1_RE | USART_CR1_TE; //Receiver enable, Transmitter enable, USART disable

    USART3->BRR=0x9C4;//9600 at 24Mhz

    USART3->CR1 |= USART_CR1_UE;; //Uart Enable;

while (((USART3->SR) & USART_SR_TXE)==0);

   USART3->DR = 'S';

IWDG->KR = KR_KEY_Enable;

  while(1)

  {

    IWDG->KR =KR_KEY_Reload;

   if (((USART3->SR)&USART_SR_RXNE)>0)

    {

    byte_temp= USART3->DR;

     if (((USART3->SR)&USART_SR_TXE)>0)

     {

       USART3->DR =(byte_temp+1);

       while(1);//reset here

     }

    }

 /*   while(TxCounter < 30)

  {

     USART3->DR =('5');

      while(((USART3->SR)&USART_SR_TXE)==0);// Loop until USARTy DR register is empty

      TxCounter++;

  }

  TxCounter=0;*/

  }

}

void setsystemclock(void)

{

      RCC->CR |= RCC_CR_HSEON;

    // Wait until it's ready

    while ((RCC->CR & RCC_CR_HSERDY) == 0)

        ;

    // Select PREDIV1 as PLL source and sett PLL mul to 3 (set bit 0)

    // for 8*3 = 24 MHz

    RCC->CFGR |= RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL_0;

    // Start PLL

    RCC->CR |= RCC_CR_PLLON;

    // Wait until it's ready

    while ((RCC->CR & RCC_CR_PLLRDY) == 0)

        ;

    // Select PLL as system clock

    RCC->CFGR |= RCC_CFGR_SW_PLL;

    // Here we can check if PLL is used, and maybe disable HSI

    // Disable HSI

    RCC->CR &= ~RCC_CR_HSION;

    RCC->CFGR|=RCC_CFGR_MCO_2; //sys clock output

}

[ezrab]

Posted on October 21, 2010 at 09:00

never mind it works i tried it on adiffrent board and it works.

i dont know what can be wrong with the older board but there is always stack full there.

tried to erase the flash didnt help.

mybe its becuse i removed the SB16?

[ezrab]

Posted on October 21, 2010 at 09:53

i checked and it is realy becuse SB16 was missing now the older board works to.

i wonder why SB16 effects like that?