VSSA/VDDA is not connected to VSS/VDD

[Robert Amann]

Posted on December 11, 2017 at 15:14

Hello,

we're currently investigating a problem with one of our products, which seems to stall sporadically at a customers site. The used controller is STM32F103VE. I've detected at least one potential problem in our design, because VSSA/VDDA are seperated from VSS/VDD by an independant, galvanically isolated 3.3V power supply.

Of course, the manuals point out that these power supply domains should be connected. But what are the possible problems if this was done wrong as in our design? Could this cause a stalled controller?

#stm32f103xx #grounding

[waclawek.jan]

Posted on December 12, 2017 at 09:44

The requirement to have them connected (or be within a small margin to each other, 50mV or so, see DS) is there for a reason. I'd expect problems up to damaged chip if the VSS-to-VSSA and/or  VDD-to-VDDA differences are larger than a few hundreds of mV.

JW

[AvaTar]

Posted on December 12, 2017 at 10:30

Galvanically isolated supplies make no sense IMHO.

VSS and VSSA are definitely connected internally. They have just separate terminals to avoid transverse currents through analog components.

[waclawek.jan]

Posted on December 12, 2017 at 11:02

VSS and VSSA are definitely connected internally.

Not necessarily in a low-ohmic resistive way, see the 50mV allowed between VSS and VSSA ( in a more general way, specified as |VSSX  − VSS| ) by DS (read: there may be a silicon protection structure between them, for example, and otherwise isolated).

JW

[Jack Peacock]

Posted on December 13, 2017 at 02:54

Have you checked the rise times on your 3.3V power supplies?  The analog section is also used with the PLL so your suspicion does fit, possible the clock isn't running or something in RCC is damaged.  Or you may be coming out of reset with VDD above threshold before the VDDA is in spec.  As I recall there's a minimum VDDA voltage when the BOR threshold starts the core, but not sure about the F1 series, haven't used them in several years.

  Jack Peacock

[Robert Amann]

Posted on December 14, 2017 at 10:49

Thanks for your help.

Yes, I'm with ​ regarding the nonsense of a galvanic isolation at this point. It's a faulty design and we won't do that again. The question is if this explains the problems that our customer gets with our device.

I haven't checked the 3.3V rise times yet, but that's a good hint. On the other hand, the problem occurs at an indefinite time after the device is up and running.

[AvaTar]

Posted on December 14, 2017 at 11:12

Problems occur when the potential difference exceed a threshold level.

And Jack Peacock might be right about the primarily affected peripherals, I have never experimented in that direction.

However, have you already ruled out a software issue ?

Stack overflows or race conditions involving interrupts can be as spurious as mains/power supply interferences.