using the TIMER2 ETR input in reset mode for stm32F446RE

[papageno]

Hi everybody,

i would like to use the STM32F446 Timer2 with one external input to reset the counter (avlue to 0), then having an input capture to read the timer value between two consecutives reset thru ETR input. Input capture settings is not a problem and works fine, the event happens regularly at the iC4 frequency but as I can see the counter does not reset on ETR input.

my settings Reset Mode, signal on ETR, internal clock, signal on IC4, call back on IC capture.

What i would like to do with the counter:

t0 -> ETR signal goes down and on rising edge CNT = 0

t1 -> IC4 signal read CNT value

t2 -> IC4 signal read CNT value

...

tm -> IC4 signal read CNT value

t0 + N -> ETR signal goes down and on rising edge -> CNT = 0

....

and so on.

Is there a way to see that the ETR input was really active and put the timer CNT to 0 ??? is it possible to generate an Irq on that event ? Sending the CNt on an UART is not really convincing.

By advance I thank you guys.

PP

[waclawek.jan]

Read out and check/post the TIM and relevant GPIO registers.

Reset from slave-mode controller should generate Update event (thus interrupt).

JW

[TDK]

If you just want to measure the time between events, you don't need to reset the counter. Let let it free flow up to the max value and subtract to find the difference. Overflow is taken care of in this operation.

There isn't an interrupt for ETR, but you could configure the pin with an EXTI interrupt.

[papageno]

Thank you guys for your answers but I do need to reset the counter on ETR then start to measure time from that moment when the counter is reset. I thought I could use the ETr input when in reset mode but I canot see it working so far, so I will need to use the signal in irq, stop the counter, write 0 in it then start it again so that the input cpature can give me the apporiate timer value on each Input capture.

[waclawek.jan]

Read out and check/post the TIM and relevant GPIO registers.

JW

[papageno]

Jan,

Looks like the UG (update generation) bit from TIMx_EGR is set when the CNT register is reset .... So thank you.