Using spi slave mode,hardware nss setting. Is shift register cleared at nss rise edge?

[TMats.9]

I am using spi slave mode,hardware nss setting.

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​when cs is low,if there are a lot of clocks due to noise,

Is shift register cleared at the rising nss edge?

[TDK]

Is NSS is low, SCK toggling due to noise or anything else will be interpreted as clocks and data will be shifted out accordingly. If NSS is high, edges will be ignored.

Edit: I do believe shift register is cleared when NSS transitions high but can't find it stated in the RM.

[TMats.9]

Thank you for your answer.

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I thought, when nss is high,the shift register would be reset automatically,is that wrong?

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​I want to reset the result of an accidental shift out shift register,when nss is high.

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When SCK toggling due to noise or anything else will be interpreted as clocks and data will be shifted out accordingly,

how should I clear shift register?

[TDK]

I think it is (see edit) but you can for sure clear it by disabling/reenabling the peripheral.

[S.Ma]

Nss will tristate the io, so it disconnect the spi from external signals. I think it does not clear anything. Some spi with fifo filled by cyclic dma will remain queued while nss is high, and user will see previous data pushed on the next transaction 4 bytee. Peripheral disable wont help. Sw.reset in syscfg/rcc will.

[David Littell]

If you have that much noise while CS is asserted your data is probably garbage anyway.

Fix the real problem - the noise.

[TMats.9]

Thank you for your answer.

I have resolved.

I tested it on MCU, when NSS was asserted,shift register was reset.