Using Level Triggered Interrupts on STM32F4 and other devices

[canbu22]

Posted on January 23, 2014 at 18:40

Hi,

All EXTI-External interrupts  on STM32Fxx and other STM32 devices implemented by STM are EDGE triggered interrupts.

The ARM core however supports Level, Pulse and Edge triggered interrupts. STM32Fxx Tech.Ref.Manual mentions briefly about this and suggests to refer to ARM's CPU Tech.Ref.Manusl. But there too it is not clearly documented, in fact very little info is available.

I need to implement a Level triggered interrupt scheme, where as long as the external signal is active, the ISR would get executed multiple times repeatedly with out much over heads, till the termination condition is met. (for eg : continuous key press events in a keyboard scan).

STM's firmware libraries don't have any support for these Level sensitive interrupts or I can not find any for direct ARM core related interrupts.

Does any one know how one can implement these on STM32F4xx devices or any documentation/library available?

Thanks,

Anbazhagan

#stm32 #level-triggered-interrupts

[Tesla DeLorean]

Posted on January 23, 2014 at 19:00

No, getting stuck in interrupt context while someone holds a pin down would preclude foreground execution.

Suggest you have a 1 KHz (1ms) SysTick, and poll your levels there.

[canbu22]

Posted on January 23, 2014 at 19:23

It depends upon the application and which events you want to handle on priority.

When you have the external level sensitive events processed at a much lower priorities, these can be further interrupted by other higher-priority events and meet your system timing requirements.

Yes, polling would work but it is an inefficient scheme to sit on an idle loop (even if one does it in ISR after initial event detection)