Use of VREFBUF on the STM32H753.

[JMall]

The voltage reference buffer (VREFBUF) seems to control what happens with the Vref+ pin, as described in this from the Reference Manual:

Table 225. VREF buffer modes

ENVR HIZ VREF buffer configuration

0 0

VREFBUF buffer OFF:

– VREF+ pin pulled-down to VSSA

0 1

External voltage reference mode (default value):

– VREFBUF buffer OFF

– VREF+ pin input mode

1 0

Internal voltage reference mode:

– VREFBUF buffer ON

– VREF+ pin connected to VREFBUF buffer output

1 1

Hold mode:

– VREFBUF buffer OFF

– VREF+ pin floating. The voltage is held with the external capacitor

– VRR detection disabled and VRR bit keeps last state

This says that 0,1 is the default (which is what I want), but when I read those bits they are always 0,0 -- even just after I've tried setting HIZ with:

HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE);

And a setting of 0,0 is supposed to pull the Vref+ pin down to Vssa, which really doesn't seem to be what it's doing.

My question is basically how this all really works?

Thanks.

[MasterT]

I find same issue on my nucleo-H743ZI, reading VREFBUF_BASE returns "0", writing to the register doesn't work, and noise level I'm getting out of DAC and ADC is unacceptable high.

Is there errata somewhere, that may explain work around?

[ColaChugger]

H743ZI has a lot of noise on PA1 pin (and maybe more, but thats the one that bothered me). So much, that it affects neighbor-pins as well. Fiddled with the GPIO-settings to reduce the noise. Just try using a different pin.

[MasterT]

Different pin is not an option with DAC output, it's hardwired to PA4 & 5. GPIO port settings is also has no effect. I already verified same code on nucleo-F767, and get pretty good results. As F767 has no VREFBUFF , it's make me believe that hardware faults with VREFBUF on H743ZI is the only suspect with high noise issue I'm having.

[ColaChugger]

I'm also using 2 DACs. But there haven't been any issues for me yet. What kind of noise level are we talking?

[MasterT]

I have AD7984-pmdz https://wiki.analog.com/resources/eval/user-guides/circuits-from-the-lab/pulsar-adc-pmods

connected over SPI, 18-bits ADC running at 1 MSPS. H743 than does 8192-FFT, so technically I should say "relatively high" noise level - relatively to other STM mcu products with similar 12-bits DAC. On average, I observed -80...-84 dBc noise floor out of F446RE, F303RE, F767ZI, but H743 provides about 30 dB more, about -50...-54 dBc. What I also noticed, noise level slightly different between channel 1 & 2, more intense from PA5, seems not Gaussian - more likely from digital domain with regular short pulses wide band source.

DAC is configured with output buffer disabled, according to AN4566 Application note, AD4891-2 OPA is used as external amplifier-filter, 4-th order LPF.

[DShar.17]

dear ST Employees,

can we please get an answer from ST about this issue? Like Jim, above, no matter what value I write to the VREFBUF->CSR, I always read back 0. We're using an external reference in our application, and indeed it seems that the MCU's Vref+ pin has an internal pull down to Vss: our reference voltage is drooping (2.035V) below the expected value of 2.048V.

Looking forward to hearing from ST.

Thanks,

-Dan

[waclawek.jan]

What's the state of RCC_APB4ENR.VREFEN?

JW

[DShar.17]

Ah, interesting .. it is 0. When I set it to 1 through the debugger, voila! ... VREFBUF-CSR = 0x02.

Many Many thanks JW!

-Dan

[waclawek.jan]

And the pin's observed state did change accordingly, @Community memberharon​ ?

I don't use a 'H7 and am curious.

JW

[DShar.17]

Ah, good question - no it did not. This implyies that the peripheral was behaving as advertised (initialized to default state), but we just couldn't tell ... without the RCC enabling it, communication with it was disabled. But now I can change the pin state: with HIZ disabled, the voltage drooped way more.

[DShar.17]

there's even a handy __HAL_RCC_VREF_CLK_ENABLE() call