understanding the connectivity clock tree

[janvi2]

Posted on September 12, 2010 at 23:39

understanding the connectivity clock tree

[Tesla DeLorean]

Posted on May 17, 2011 at 14:06

What is the diffrence between the signal PLLCLK and PLLVCO ?

One is DOUBLE the other.

My copy of RM0008 (Rev 11) clearly indicates that PLLVCO = 2 X PLLCLK, and that PLL3VCO = 2 * PLL3CLK

The VCO (Voltage Controlled Oscillator) which the PLL is pumping up/down in frequency to achieve the desired rate using the HSI/HSE as a baseline reference. The VCO works at twice the PLL output to ensure that the mark/space ratio of the output clock is 50:50

The PLL design is almost certainly capable of frequencies significantly higher than the logic portion of the STM32. I have ten year old CMOS SoC designs with PLL's in the 300 MHz region.