Understanding STM32F0 GPIO Interruts

[Guido Körber]

Posted on February 02, 2018 at 22:35

Not sure if I understood the GPIO interrupt structure of the STM32F0 family correct.

I can select either i.e. PA0 or PB0 as interrupt source but not both at the same time?

[Tesla DeLorean]

Posted on February 02, 2018 at 22:40

Correct. So you can have PA0, PB1, etc. Lower numbers having higher priority in the STM32 world, higher number are grouped together so the IRQ Handler must decode/dispatch multiple sources.

[Guido Körber]

Posted on February 02, 2018 at 22:50

Awww, this sucks. I need the interrupt for remote wakeup of a USB device. The inputs which can cause the wakeup are spread out over PA and PB, using most of the pins on both. So now I have to select just certain ones that will be able to wake up the host.

I am a big fan of just a bitfield as a mask for this purpose…

[henry.dick]

Posted on February 02, 2018 at 22:56

Your reading of it is absolutely correct. That's single handedly the worst design feature stm has in it's stm8 and stm32 families. Bar none.

[Guido Körber]

Posted on February 02, 2018 at 23:04

Actually that design is so strange it took me quite while to understand it but I had to ask here to believe it…

[henry.dick]

Posted on February 03, 2018 at 00:11

yeah. when I first started to look at those parts, it took me more than a few times to confirm what I read is true, as you did.

the saddest part is that there is absolutely no reason, conceivable to anyone other than st, for them to have done to one an otherwise fine chip.

the SPL i2c on earlier chips and subsequent 'fix' from ST are another fiasco that I think st would love to forget.