Unable to use QuadSPI Status Flag Polling Mode with instruction on 4 lines on STM32H753
I am having issues getting the status flag polling mode to work when I try to poll with a QuadSPI command that uses all four data lines for the instruction. When using a command with a 4-line instruction in this mode, it polls the first command correctly, but the second command has one fewer clock cycles than expected, and then the chip select never goes high again. I've tried getting this to work with multiple configuration settings, but the common denominator seems to be the 4-line instruction causing the issue.
QSPI_HandleTypeDef hqspi =
{
.Instance = QUADSPI,
.Init.ClockPrescaler = 63,
.Init.FifoThreshold = 1,
.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_NONE,
.Init.FlashSize = 1,
.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_1_CYCLE,
.Init.ClockMode = QSPI_CLOCK_MODE_0,
.Init.FlashID = QSPI_FLASH_ID_1,
.Init.DualFlash = QSPI_DUALFLASH_DISABLE,
};
QSPI_CommandTypeDef qspiCmd =
{
.Instruction = 0x05,
.Address = 0x00000000,
.AlternateBytes = 0x00000000,
.AddressSize = QSPI_ADDRESS_24_BITS,
.AlternateBytesSize = QSPI_ALTERNATE_BYTES_8_BITS,
.DummyCycles = 0,
.InstructionMode = QSPI_INSTRUCTION_4_LINES,
.AddressMode = QSPI_ADDRESS_NONE,
.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE,
.DataMode = QSPI_DATA_4_LINES,
.NbData = 1,
.DdrMode = QSPI_DDR_MODE_DISABLE,
.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY,
.SIOOMode = QSPI_SIOO_INST_EVERY_CMD,
};
QSPI_AutoPollingTypeDef autoPollCfg =
{
.Match = 0x12345678, // Don't match, continue polling indefinitely
.Mask = 0xFFFFFFFF,
.Interval = 1,
.StatusBytesSize = 1,
.MatchMode = QSPI_MATCH_MODE_AND,
.AutomaticStop = QSPI_AUTOMATIC_STOP_DISABLE,
};
HAL_QSPI_Init(&hqspi);
HAL_QSPI_AutoPolling(&hqspi, &qspiCmd, &autoPollCfg, HAL_MAX_DELAY);The above code produces the following output:
(Ignore the actual data being read)
Changing only the number of instruction lines seems to produce correct polling:
.InstructionMode = QSPI_INSTRUCTION_1_LINE,
.InstructionMode = QSPI_INSTRUCTION_2_LINES,