Unable to freeze IWDG during debugging using SEGGER j-link (STM32L053)

[SMoon.2]

I've configured IWDG for my application (STM32L053). When I've halted the application during debugging, the IWDG is still triggering resets. I'm using a SEGGER j-link.

I've attempted to use the __HAL_DBGMCU_FREEZE_IWDG() macro, but it doesn't seem to have any affect. I've also tried to write to the register directly:

*((volatile int *)(0xE0042008)) |= (1 << 12);

When I check in the SFR view for APB1_FZ, the DBG_IWDG_STOP value never changes.

I can disable initializing the IWDG when debugging, but that isn't ideal. Any help?

[SMoon.2]

Issue was DBGEN bit 22 in the RCC_APB2ENR register must be set to enable the DBG clock before writing to the DBG_APB1_FZ register.

Once the bit was set I was able to use __HAL_DBGMCU_FREEZE_IWDG() to set the DBG_IWDG_STOP bit and watchdog successfully froze while application was halted.