UART RS485: Driver enable state during IDLE frame generation

[Gael Le Moing]

Hi everyone,

I am using STM32H753 UART along with RS485 transceivers for a half-duplex bus (each node transmits one after the other), and I noticed that although the TE bit is set to generate the IDEL frame before starting any message transmission, it appears the IDLE state is not visible by observing the bus line (after the RS485 transceiver). But, according to the delay between a command and a response, I think the duration of the IDLE byte is here on the line, but just not visible.

As the RS485 transceiver takes Driver Enable pin managed directly by the STM32 UART peripheral, I am wondering if the DE pin is driven High as soon as it needs for the IDLE frame to be visible on the line.

If someone from ST could clarify what is the supposed behaviour of the UART/USART logic, it would be greatly appreciated.

To STM32 users: did anyone observed the same thing? How did you manage to enforce a visible IDLE frame on the line?

Thanks,

Gael

[waclawek.jan]

> it appears the IDLE state is not visible by observing the bus line

While it may be that DE is not driven during the IDLE frame, normally RS485 buses should be driven to log.1 by fail-safe circuitry (usually pullup/pulldown network), so it should not matter whether IDLE is driven or not.

JW