TIMx_ARR relations to the preload and shadow register?

[KSun.11]

In RM0008 Technical Reference Chapter 15, TIMx_ARR was introduced in counting mode. Meanwhile, two other registers: preloaded and shadow register, were also mentioned. However, in the TIMx register Map, Preloaded and shadow registers were not mentioned at all. I can roughly understand how those two registers work with the ARR preloaded register.

But what about shadow? So ARR value will follow whatever in the shadow register or what?

Someone please help ~

[berendi]

The register map documents only the registers visible to the user program.

There is the ARR register that you can write, and an unnamed shadow register. Let's call it ARR_sh for now.

The CNT register is checked against ARR_sh when counting up, or reloaded from ARR_sh when counting down.

And there is a bit in the CR1 register called TIM_CR1_ARPE, which controls when ARR will be copied to ARR_sh.

If TIM_CR1_ARPE == 0, writing ARR goes immediately to ARR_sh.

If TIM_CR1_ARPE == 1, ARR is copied to ARR_sh at the next update event.

 The same logic is present in the compare registers TIM_CCR{1-4}, controlled by the TIM_CCMR{1,2}_OC{1,2,3,4}PE bits.

The prescaler register PSC has a shadow too, and it is always enabled.

[KSun.11]

Thanks, Berendi,

So is that right to say, the shadow register is the one the processor uses for indicating the reload value?

Then I won't struggle about why not introducing these two registers, or the preload and shadow register relations to the ARR. I should just take it as how the system works. ​

[KSun.11]

Found this section on General-Purpose Timer Cookbook from ST (application note AN4776). That helps to clarify my doubts. So just to share here in case anyone having similar doubts.

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