Timers break and clear behavior in general

[EAlek.11]

Hello. I can't fully understand break and clear funtionality of timers on STM32. In read dasheets and tryed various options for break and clear inputs, but in general it worked in a similar way:

It puts timer output to predefined state untill it overflow (untill next timer period).

And it's not very convenient. In my application timer work in one pulse mode with DMA to generate complex sequences from memory on the haptic motor. Many impulses generates on timer output in ONE TIMER PERIOD. And i want to configure break or clear funcionaluty to put timer output in predefined state and release it asynchronously with timer regardless of its overflow. Is it posible?

[waclawek.jan]

> It puts timer output to predefined state untill it overflow (untill next timer period).

That's how clear works.

After *break*, outputs are automatically resumed only if BDTR.AOE is set.

JW

[EAlek.11]

It was set in my application. Timer output holds good, but releasing only on timer update event. In my reference manual (STM32G431) it described as:

Bit 14 AOE: Automatic output enable

0:MOE can be set only by software

1:MOE can be set by software or automatically at the next update event (if none of the break inputs tim_brk and tim_brk2 is active)

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

Any other ideas?

[waclawek.jan]

Don't set it.

JW