timers and clocks

[lior]

Posted on January 28, 2008 at 15:51

timers and clocks

[lior]

Posted on May 17, 2011 at 12:22

thanks for your answer.

but how i multiply the TIMER x2.

which register do this?

[lior]

Posted on May 17, 2011 at 12:22

hello,

i tried to run the example1 of the TIM in the FWLIB and it is work correct but there is something that i dont understand APB1 (PCLK1) IS DIVIDED by 4 so the TIM 2,3,4 clock is 72M/4 = 18M but I see that the clock of the timers is 36MHZ.

please tell me what i miss here to understand this?

please see this configuration (for the example1 in TIM libary)

/* Enable Prefetch Buffer */

FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);

/* Flash 2 wait state */

FLASH_SetLatency(FLASH_Latency_2);

/* HCLK = SYSCLK */

RCC_HCLKConfig(RCC_SYSCLK_Div1); //APB Low speed prescaler

/* PCLK2 = HCLK */

RCC_PCLK2Config(RCC_HCLK_Div1); //PCLK2 NOT DIVIDED

/* PCLK1 = HCLK/4 */

RCC_PCLK1Config(RCC_HCLK_Div4);//PCLK1 = HCLK/4

/* PLLCLK = 8MHz * 9 = 72 MHz */

RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);

/* Enable PLL */

RCC_PLLCmd(ENABLE);//turn on the PLL

[16-32micros]

Posted on May 17, 2011 at 12:22

Hi lior.b,

Yes, this is possible. You should modify the multiplier from x2 to x1 before the Timer clock input to have 18MHz.

STOne-32.

[lior]

Posted on May 17, 2011 at 12:22

hello ,

thanks again .

i find it and i understood it

thank you very much.

[16-32micros]

Posted on May 17, 2011 at 12:22

Here you go : Page 50 of the reference manual.

[sstasiak]

Posted on May 17, 2011 at 12:22

This finally makes sense to me. I've been scouring the manual for a couple of hours now trying to find something that confirms your statement. Can you tell me which section I should look at closer ?

btw: this is my first experience w/st mcu's and I'm quite impressed so far, just looking forward to an stm w/an external mem interface.

[16-32micros]

Posted on May 17, 2011 at 12:22

Quote:

On 23-01-2008 at 18:17, Anonymous wrote:

Hi lior.b,

Yes, this is possible. You should modify the multiplier from x2 to x1 before the Timer clock input to have 18MHz.

STOne-32.

Dear lior.b,

Sorry for the confusion, I made a mistake ,in fact This is fixed automatically by hardware to x2 when APB prescaler is different from 1 and is equal to one when APB Prescaler is = 1. So to have a 18MHz you should configure your AHB clock to 18MHz anndAPB = 18MHz but this is not efficient. Hope this clarifies more. STOne-32

[sjackson]

Posted on May 17, 2011 at 12:22

Nevermind. I see now that the prescaler is actually the specified value plus one, giving 36/5 = 7.2MHz.

[sjackson]

Posted on May 17, 2011 at 12:22

In example number 5 for TIMx peripherals in the FW library, there is this comment block:

/* ---------------------------------------------------------------

TIM2 Configuration: Output Compare Timing Mode:

TIM2CLK = 36 MHz, Prescaler = 4, TIM2 counter clock = 7.2 MHz

CC1 update rate = TIM2 counter clock / CCR1_Val = 146.48 Hz

CC2 update rate = TIM2 counter clock / CCR2_Val = 219.7 Hz

CC3 update rate = TIM2 counter clock / CCR3_Val = 439.4 Hz

CC4 update rate = TIM2 counter clock / CCR4_Val = 878.9 Hz

--------------------------------------------------------------- */

Where do they get 7.2MHz from if the main clock is 72MHz and prescaler for APB1 clocks is 4, TIM2CLK is indeed 36MHz but 36/4 = 9, not 7.2.