timer capture compare

[psandesh007]

Posted on June 24, 2013 at 15:22

Im going to capture simultaneously 4 input signals(same inputs for 4 channels) using Timer 8 by enabling all the interrupts in TIM->CCER register .. But it was not capturing correctly and im getting  channel number  2 and 4 continuously compared to 1 and 3 channels while im giving same frequency for all the channels..

please help me to solve this problem..

[psandesh007]

Posted on July 01, 2013 at 15:25

Im still in problem to capture the accurate frequency of cascaded two timers please help me to overcome this problem ..

        ch4_CAP=TIM3->CCR1;

        ch4_CAP2=TIM1->CNT;

        if(ch4_CAP2>=ch4_CAP3)

        {

            gl31_captval_CH4=((65535*ch4_CAP2)+ch4_CAP)-((65535*ch4_CAP3)+ch4_CAP1);

        }

        else

        {

               ch4_CAP3=65535-ch4_CAP3;

            gl31_captval_CH4=(65535*(ch4_CAP2+ch4_CAP3))+(ch4_CAP-ch4_CAP1);

        }

        ch4_CAP1=TIM3->CCR1;

        ch4_CAP3=TIM1->CNT;

I tried in so many ways but still the frequency was fluctuating (all channels frequencies  are fluctuating at the same time)

[Tesla DeLorean]

Posted on July 01, 2013 at 17:13

It's a bit of a mess, some of the logic/math is backward, and count should be 65536. This is compounded by a race condition because the high order counter isn't latched, but incremented by a free running counter.

I would use the timer to get the low order precision, and use a high precision, high rate 32-bit counter to mark time and obtain the high order difference.

[Tesla DeLorean]

Posted on July 01, 2013 at 23:39

This is a blind implementation, as there's no code framework. Assumes TIM3 is slaved off TIM1, and Period=65535; (N-1)

uint32_t captured[6];
void TIM3_IRQHandler(void)
{
uint32_t timebase;
uint16_t timehigh1, timehigh2, timelow;
do
{
timehigh1 = TIM3->CNT; // High order, 1/65536th rate on slave
timelow = TIM1->CNT; // Low order, high rate, will change by a dozen or so ticks
timehigh2 = TIM3->CNT; // Catch rollover, if it occurred
}
while(timehigh1 != timehigh2); // Overflowed, try over, perhaps 1 additional iteration
timebase = ((uint32_t)timehigh1 << 
16
) | (uint32_t)timelow;
// Then for each channel
if (TIM_GetITStatus(TIM3, TIM_IT_CC1) == SET)
{
uint16_t 
ccr
= 
TIM3
->CCR1; // note use of local/static with same names to limit typos
static uint16_t ccrlast;
static uint32_t timelast;
uint32_t timedelta, ccrdelta;
/* Clear TIM3 Capture compare interrupt pending bit */
TIM_ClearITPendingBit(TIM3, TIM_IT_CC1);
timedelta = (timebase - timelast) >> 16; // error perhaps a few 100 cycles, but we truncate by 65536, so just rounding noise
timelast = timebase; 
ccrdelta = (uint32_t)(ccr - ccrlast); // implicitly & 0xFFFF 
ccrlast = ccr;
captured[4] = ccrdelta + (timedelta << 16); // Use an array! inherit channel 4 designation
} // [e-mail]

// ..
}

Now there is at least one flaw in this method, if the period of the input signal is close to the 16-bit overflow it might underestimate. One way of addressing this would be to compute a rough delta, and compare that to the fine computation. If the rough estimate was around 60000 cycles more, then you have identified a cycle slip in the high order and would correct the fine computation with a += 655

[psandesh007]

Posted on July 03, 2013 at 07:00

Thank you clive im trying still.

[psandesh007]

Posted on July 09, 2013 at 14:34

I got it. i was not given the frequency for the slave timer .. Now it is cleared.. thank you..