This can be realized with DAC and ADC in STM32F103?

[wc40]

Posted on March 01, 2016 at 16:52

DAC is used for generating sinus wave 1kHz.

1000 sample is over DMA transferred on DAC 1MHz/1000SPS = 1kHz

It would be good to start each sinusoid nullify one of the counters.

This signal, after passing through something DUT return on ADC

After generated fifty sinus wave is started ADC and over DMA make 1000 measure on 1MHz

What is the purpose?

Determine the attenuation and shift waves at DUT.

Rapid

insight into

the datasheet

no problem

,

but

rather

ask:

[Tesla DeLorean]

Posted on March 01, 2016 at 17:57

I looks plausible, just, for a 72 MHz F1, there are likely better choices to get a more stable 1MSps

[wc40]

Posted on March 01, 2016 at 20:34

I thought about

STM32F103RD on 56MHz, R

due to 64kB RAM and 56MHz

because

max ADC fadc is 14MHz.

[AvaTar]

Posted on March 02, 2016 at 08:18

> This can be realized with DAC and ADC in STM32F103?

 

In theory, yes.

However, ST's DAC implementation has settling rates of about 4 .. 5 us (check the datasheet), you will hit a bandwidth limit here.

[wc40]

Posted on March 02, 2016 at 10:43

The devil is in the details.

In datasheet say t setting =3-4us Settling time (full scale: for a 10-bit input code transition between the lowest and the highest

input codes when DAC_OUT reaches final value ±1LSB.Expressed in angles, Setting from 0 to 1/2PI and for load R=5kOhm C=50pF.

For my sinus wave have transition 250 point to 1/2PiIf use external amplifier for example AD8628

total setting time =Sqrt(tsDAC^2 +tsAMP^2)= Sqrt (4^2+3.3^2)=5.2us max and 4.5us Typ,

for code transition from 0 to 4096, 5.2/4096 = 1.27ns/LSB. Biggest change in my sinus wave is 13LSB 16.5ns.

[AvaTar]

Posted on March 02, 2016 at 12:27

> The devil is in the details.

 

Yes, you need to check it for your own application.

Just wanted point out the fact that you can feed the DAC DR register much faster than the output can follow. A 3db-bandwidth of 1.0 MHz (or 500kHz) is unrealistic.