The difference between VREF+ and VDDA of STM32F407

[捷鄭.1]

Is the following note quoted from the specification of STM32F407 applied to all the time from power-up or just during the period when the analog data is being sampled?

「4. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V. �?

[Peter BENSCH]

Welcome, @�?� 鄭​, to the community!

the note applies to the entire time when Vref is present and not only when analog data is sampled.

Regards

/Peter

[捷鄭.1]

Thanks for your prompt reply.​ Then I will generate Vref and VDDA from the same source.