The behavior of the​ gpio pin when powering on and powering off

[diverger]

This question may applied to the whole STM family and maybe pure hardware related, but I expect someone can give some clues.

​

1. May I safely assume the gpio pins are ​high impedance when powering on?
2. If I set pin to output, and output a high. Then, the power supply goes down. I expect the output will track the power supply till some point, that the pin can't retain output state anymore. Am I right? If so, when the point will occur, what's the supply voltage then?
3. Similar to above, but this time set the pin low. What's the point I can't safely assume the pin is low?

Thanks.​

[TDK]

> May I safely assume the gpio pins are ​high impedance when powering on?

Most pins are in input mode, which is floating. Some pins associated with JTAG/SWD are not floating.

> If I set pin to output, and output a high. Then, the power supply goes down. I expect the output will track the power supply till some point, that the pin can't retain output state anymore. Am I right? If so, when the point will occur, what's the supply voltage then?

Yep. The brown-out reset (BOR) is configurable and kicks in at various states, but generally around 1.8V. Once in reset, pins are in their reset state.

> Similar to above, but this time set the pin low. What's the point I can't safely assume the pin is low?

Same as above.

[berendi]

Check the reset values of the GPIO registers in the reference manual to see which pins have pullup or pulldown enabled.