Teach me STM32F4, DCMI interface, when DCMI data is saved at the external SRAM.

[jiung78]

Posted on October 24, 2016 at 15:02

The original post was too long to process during our migration. Please click on the attachment to read the original post.

[waclawek.jan]

Posted on October 24, 2016 at 19:00

> The read/write test of Sram works properly.

What exactly does that mean?

>        DMA_InitStructure.DMA_Memory0BaseAddr =(u32)FSMC_IMAGE_ADDRESS;

Is this address aligned to word or halfword?

>       DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;

Try Word here - the FSMC should be able to split word accesses on the AHB side into halfword accesses on its external side.

>       DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;

Try lower threshold.

Is there anything else running on DMA2?

JW