SWD layout

[cmackinnon]

Posted on June 12, 2014 at 00:53

Does ST have any layout recommendations for using their Serial Wire Debug capability?  We are planning on using the Cortex M ETM debugging functionality.  This includes using the TRC CLK, TRC DATA[0], TRC DATA[1], TRC DATA[2], TRC DATA[3] and TRC DATA[4] signals.  I understand that these can be high speed and may need special layout considerations.

Thanks for your help!

#swd-layout

[Tesla DeLorean]

Posted on June 12, 2014 at 02:40

I'm not sure I've seen any recommendations, and most connectors I've seen have traces running 3-4'' and in some cases through jumpers. I would just recommend you keep them all roughly the same length, and don't create large T connections.

Looks at the STM324xG-EVAL, STM324x9I-EVAL and MCBSTM32F400.

I've not played with trace much, I have ULink-Pro and J-Trace pods, they can be useful to diagnose the ''How the heck did it get here'' scenarios, and fine grain profiling. The DWT_CYCNT in the core can be very useful for benchmarking.

If you have large memories you do lose 3 of the high order address bits. The design with jumpers breaks the connection to the memory address bits, and replaces them with a 10K pull down resistor on the now disconnected memory side.

[ducommun]

Posted on August 07, 2014 at 10:00

The length of the 4 pin trace must be as short as possible.

The ST eval kit have an issue and can't work at more than 50 MHz, ST tell we must remove ESD protection and resistor with shared signal on ETM pin, but there is a real issue with this eval board.

Keil tell that their eval board doesn't have this kind of issue and can run at full speed.

But I'm not an hardware developer, I can't help you for the layout.

[jpeacock2399]

Posted on August 08, 2014 at 21:18

In my experience what works for JTAG also works for SWD.  I use a 10 pin 2mm header, short traces about 4cm at most, with 10 ohm resistors in series between each JTAG/SWD pin and the header, and a 0.1uf cap across power and ground at the header.  I use an F4 so no pull-ups needed.  I don't put any ESD or TVS diodes on the JTAG port.

Both JTAG and SWD work fine with a Segger J-Link.

  Jack peacock

[Tesla DeLorean]

Posted on August 09, 2014 at 06:54

The trace port is the 20-pin 0.5'' pitch Cortex Debug + ETM 

http://www2.keil.com/coresight/coresight-connectors/

The ULink Pro and JLink Ultra have significantly higher bandwidth than the usual pods. The ULink Pro uses USB 2.0 HS and an FPGA.

[jj2]

Posted on August 10, 2014 at 14:38

''The trace port is the 20-pin 0.5'' pitch Cortex Debug + ETM...''

Of course a typo - referenced port is far more usable/attractive @ 0.05'' pitch...  and 10 pin JTAG/SWD port also employs that most welcome, reduced pitch footprint...