Suspecting document mistake in RM of STM32L475

[Harish1]

In the attached image showing the description of the reference manual of stm32L475. Here, it is showing the EOC flag is set to clear by the SW. We can clear the flag but how can SW set the EOC flag. I am suspecting this as a bug in the document.

Can anybody help me, whether I am right or not?

[Imen.D]

Hello @Community member​ ,

Thank you for reporting this issue.

You are right, EOC is set by HW and cleared by SW.

"The ADC sets the EOC flag as soon as a new regular conversion data is available in the ADC_DR register. An interrupt can be generated if bit EOCIE is set. EOC flag is cleared by the software either by writing 1 to it or by reading ADC_DR."

I will raise this to correct all impacted RMs.

When your question is answered, please close this topic by choosing Select as Best. This will help other users find that answer faster.

Imen

[Piranha]

Take a note that in the figure presented the EOSMP flag has exactly the same mistake.

[Imen.D]

Thanks @Piranha​ for your note.

I have taken your feedback into account for correction.

Imen