Strange, unexpected behavior of memory bus pins during reset – silicon bug in STM32H743I rev. V
Hi.
We found a serious problem in the behavior of the memory bus pins during reset.
Our design uses an STM32H743I CPU and non-volatile MRAM/FRAM memory connected via a bus. We use the FMC controller to access the memory, the bus pins are set up, and everything works. We have pull-up resistors on the nE[x] (chip select), nOE (output enable) and nWE (write enable) pins so that the correct levels are present on the memory inputs when the CPU starts. The problem occurs during a reset triggered, for example, by a watchdog or a reset button, when a negative glitch appears on these pins, causing an unwanted write to memory.
We have the same HW design equipped with STM32743I rev. Y (older than rev. V), where this problem is also manifested to a lesser extent and pull-up resistors compensate for it, but with rev. V the manifestation is significant.
The following are measurements on rev. Y and rev. V. We used the FMC_SRAM example from STM32Cube_FW_H7_V1.12.0, so we believe the FMC is initialized correctly.
Our HW with STM32H743I rev. Y (Similar measurements were observed on the STM32H743I-EVAL board with rev. Y)
PD5 – nEW – glitch from 3.36V to 3.12V
PD7 – FMC_nE1 – no glitch, stable 3.36V
PG9 – FMC_nE2 – no glitch, stable 3.36V
PG10 – FMC_nE3 – no glitch, stable 3.36V
PG12 – FMC_nE4 – glitch from 3.36V to 2.48V
Our HW with STM32H743I rev. V
PD5 – nEW – glitch from 3.36V to 0V
PD7 – FMC_nE1 – glitch from 3.36V to 1.84V
PG9 – FMC_nE2 – glitch from 3.36V to 2.12V
PG10 – FMC_nE3 – glitch from 3.36V to 1.52V
PG12 – FMC_nE4 – glitch from 3.36V to 0V
From the documentation: “During and just after reset, the alternate functions are not active and most of the I/O ports are configured in analog mode“. So it looks like when the I/O pin is transitioning to the default state, the output is set to 0 for a while.
I would like to ask ST to investigate the problem, provide a SW workaround and mention the problem in the Errata document.