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VK Verma
Associate III
May 19, 2018
Solved

Strange behavior of Port G and SPI of STM32L4+ (STM32L4R7ZIT6-144 Pin LQFP Package)

  • May 19, 2018
  • 2 replies
  • 957 views
Posted on May 19, 2018 at 06:04

Hi !

I am using STM32L4R7ZIT6-144 Pin LQFP Package on Keil-MDK, So far all other GPIO ports SET/REST test is normal except Port G with its associated SPI configuration which is neither getting SET nor RESET on push pull ,pull up mode. Although System viewer during debug mode in Keil -MDK showes normal set/reset toggle behavior for PG9/10/11/12 ports but output of the ports is not remains low and unchnaged.

I have tested VDDIO supply at pin no 131 and 95 with respect to 130 and 94 which is 3.2V.

We have tested it with three different hardware's and found the behavior same.

Due to this we are unable to use SPI3 on either of these ports.

Please advice!

Thanks and Best Regards,

VK Verma   

‌

https://community.st.com/tags♯/?tags=stm32l4%2B

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#stm32l4r7zit6 #stm32l4+
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Best answer by Tesla DeLorean
Posted on May 19, 2018 at 06:14

Haven't tried for SPI, but for UART on Port G you have to enable the VDDIO2 supply

2 replies

Tesla DeLorean
Tesla DeLoreanBest answer
Guru
May 19, 2018
Posted on May 19, 2018 at 06:14

Haven't tried for SPI, but for UART on Port G you have to enable the VDDIO2 supply

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VK Verma
VK VermaAuthor
Associate III
May 19, 2018
Posted on May 19, 2018 at 06:35

Hi Clive,

I appreciate your experience and your observation was right.

After enabling VDDIO2 both SPI and ports G are working normal.

It was very device specific function.

Once again thanks for your support.

Regards,

VK Verma  

Tesla DeLorean
Guru
May 19, 2018
Posted on May 19, 2018 at 06:39

    /* IOSV bit MUST be set to access GPIO port G[2:15] */

    __HAL_RCC_PWR_CLK_ENABLE();

    HAL_PWREx_EnableVddIO2();
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VK Verma
VK VermaAuthor
Associate III
May 19, 2018
Posted on May 19, 2018 at 08:45

HI !

Noted and problem resolved.

Thanks and Once again!

Thanks and Best Regards,

VK Verma