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peterdonchev
Senior
May 3, 2018
Solved

STMF4 USB OTG HS with embedded PHY clocks

  • May 3, 2018
  • 7 replies
  • 1588 views
Posted on May 03, 2018 at 23:59

Can someone explain me how USB HS is clocked, when using embedded PHY?

    This topic has been closed for replies.
    Best answer by waclawek.jan
    Posted on May 04, 2018 at 00:13

    From the same 48MHz clock than USB_FS.

    JW

    7 replies

    waclawek.jan
    waclawek.janBest answer
    Super User
    May 3, 2018
    Posted on May 04, 2018 at 00:13

    From the same 48MHz clock than USB_FS.

    JW

    peterdonchev
    Senior
    May 3, 2018
    Posted on May 04, 2018 at 01:05

    Hi,

    Thanks for the reply.

    Strange, currently I'm run stm32f437 at 180MHz and 48MHz clock is actually 51.2MHz, but USB is working, probably out of the specifications.
    waclawek.jan
    Super User
    May 4, 2018
    Posted on May 04, 2018 at 01:44

    Strange, currently I'm run stm32f437 at 180MHz

    Are you sure? Did you measure it?

    JW

    Tesla DeLorean
    Guru
    May 4, 2018
    Posted on May 04, 2018 at 04:06

    Some of the F4 parts have an RCC_DCKCFGR2 (F410,412,413,423,446) which can do some alternate clock/pll routing including the 'PLL48' source and SDIO

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    waclawek.jan
    Super User
    May 6, 2018
    Posted on May 06, 2018 at 16:55

    Just for my curiosity, I tested and with 45MHz clock, it still enumerate, but not every time.

    Interesting.

    Drilling down the USB standard might reveal the calculation behind the required clock precision. It surely assumes worst cases such as both parties imprecise in the opposing direction and longest possible packets, indicated also by the severely relaxed clock precision requirement for low-speed devices (1.5% for LS as compared to 0.25% for FS and 0.05% for HS) allowing to run them from ceramic oscillators rather than crystals (the former being cheaper significantly enough, by the end of past century), and enumeration is an example of such short-packets. So, working against a precise counterpart through almost perfect hardware connection, the marginal working with cca 6-7% is not shocking, but somewhat surprising nonetheless.

    Unfortunately, in the 'F437 there's no practical option to decouple the 48MHz clock from the system clock (unless you want to run the latter painfully slow). Least common multiple of 180 and 48 is 720 and he PLL can't go that high; so there's no way you can use USB  and run the SYSCLK at 180MHz.

    JW

    peterdonchev
    Senior
    May 8, 2018
    Posted on May 08, 2018 at 23:31

    Thanks for your help

    Waclawek.Jan

    , I will stick to 168MHz for sure.