STM32U5A5 Hard fault setting SYSCLK > 64Mhz

[moylando]

I'm trying to crank up the clock to Timer1 to be able to count high frequency events with better resolution.  If I set the SYSCLK to 128 I get a hard fault when my code reaches SystemClock_Config().  Even if I keep the AHB bus at the same speed (64Mhz) using prescaler.  In this case the only clock difference seems to be SYSCLK value.

Here's the first configuration which works ok:

and here's the other where it will hard fault:

Since the IDE says I should be able to take HCLK to 160Mhz which would require a much higher SYSCLK, I don't see why this SYSCLK value should cause a fault.

[moylando]

Best I've been able to manage is SYSCLK = 136Mhz, HCLK = 34Mhz, waiting for BOOSTRDY before updating the ClockConfig, then stepping up HCLK to 68Mhz.

Can't get SYSCLK past that, even leaving HCLK with /4 prescale.  And can't get HCLK to 136Mhz even doing a further wait and step.

Are hardware based issues, as in voltage or capacitance issues often found on Nucleo boards?  

[Tesla DeLorean]

Are you using a NUCLEO board, or a custom one?

Might depend what solder-bridges are made, and if jumpered to lower voltage options.

[moylando]

Hmm, page 27 of this Nucleo doc says HSE is 16Mhz.  But my CubeIDE project seemed to initialize HSE to 8Mhz.  Have I just been doing experiments in overclocking?  I'll confirm with a scope in the morning.

[AScha.3]

Board should have 16M crystal:

So your sysclock "136M" setting is 272 MHz , a bit too much for 160MHz cpu. :)

Set your clocktree with 16M HSE, and sysclk 160M , AHB div. 1 , so AHB also 160M.

 

[moylando]

An elegant and simple solution. :')  Still curious why the auto-generated code doesn't seem to follow any of the guidelines on maximum clock Hz step and BOOSTRDY flag, but that's for another day.

Thanks, all.