STM32U5A5 ADC to SRAM via GPDMA Linked List

8 replies
1360 views

I'm trying to get a continuous GPDMA transfers from ADC4 into a buffer on a Nucleo-U5A5 board. I'm not using any security settings.

It seems that the ADC conversion are working correctly. When debugging I can poll the DR and see the values change (4 potentiometers). Examining the HAL DMA channel struct always show a Locked/Busy state. List state is busy as well. I assume that's expected for a continuously running transfer?

My only problem is that the buffer I assigned for the transfer is not getting updated.

Are there any SRAM location limitations for DMA transfers on the U5A5? I've seen some references to it on other devices. Any other gotchas with GPDMA on the U5A5?

This topic has been closed for replies.

S

Sarra.S

ST Employee

Hello @moylando, welcome to ST community,

Yes, it's expected that the DMA channel will be in a locked/busy state during continuous transfers.

However, there are no specific SRAM location limitations for DMA transfers on the U5, but if the buffer assigned for the transfer isn’t 32-bit aligned, this could be the issue!

You can check this table in AN5593:

Also, it would be better to share your cubeMX configuration!

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

M

moylandoAuthor

Associate II

Thanks. I did try the 32 bit alignment for the buffer but will do a closer memory examination to make sure that is working correctly. If no change I'll post my configuration.

M

moylandoAuthor

Associate II

Thanks. I've tried this in a new project, stripped of anything but the ADC->DMA->RAM. Same outcome. What's the best format to post? Just .ioc, main.c, linked_list.c?