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Ramin1
Associate II
December 7, 2021
Solved

STM32U585QI SPI Issue

  • December 7, 2021
  • 3 replies
  • 1665 views

Hi,

I have successfully configured the SPI1 with following parameters and trying to transfer a single byte but it is being timed-out in HAL_SPI_Transmit as EOT is not being set.

Init.Mode = SPI_MODE_MASTER;

Init.Direction = SPI_DIRECTION_2LINES;

Init.DataSize = SPI_DATASIZE_8BIT;

Init.CLKPolarity = SPI_POLARITY_LOW;

Init.CLKPhase = SPI_PHASE_1EDGE;

Init.NSS = SPI_NSS_SOFT;

Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;

Init.FirstBit = SPI_FIRSTBIT_MSB;

Init.TIMode = SPI_TIMODE_DISABLE;

Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;

Init.CRCPolynomial = 0x7;

Init.NSSPMode = SPI_NSS_PULSE_DISABLE;

Init.NSSPolarity = SPI_NSS_POLARITY_LOW;

Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;

Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;

Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;

Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;

Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE;

Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE;

Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE;

Init.IOSwap = SPI_IO_SWAP_DISABLE;

Init.ReadyMasterManagement = SPI_RDY_MASTER_MANAGEMENT_INTERNALLY;

Init.ReadyPolarity = SPI_RDY_POLARITY_HIGH;

I have tried many different combinations but no success so far.

I have sourced the SPI1 by RCC_SPI1CLKSOURCE_SYSCLK and my I2C peripheral on RCC_I2C1CLKSOURCE_PCLK1 is working so I am expecting SYSCLK to be correct. I have also enabled the SPI clock in HAL_SPI_MspInit

That would be great if you could help me with this.

Thanks in advance,

Ramin

This topic has been closed for replies.
Best answer by Ramin1

Hi @Imen DAHMEN​ ,

Thanks for getting back to me, it is now working and here is the conclusion:

SPI1 was derived of Port G on our board and I had to enable VDDIO2 via PWR

3 replies

ST Technical Moderator
December 8, 2021

Hello @Ramin​ ,

The End Of Transfer (EOT) flag must be checked at the end of the communication to be sure that all data (TSIZE: number of data at current transfer) have been transmitted/received. This flag should also be checked even if the CRC is not enabled.

Did you have a look to CubeU5 example and reproduce the same issue with working SPI example?

I advise you to have a look at the STM32U5 errata sheet, to check the limitations and if you have the same conditions as described in the doc.

Check also that the RX data length is less than 1024 bytes.

When your question is answered, please close this topic by choosing Select as Best.

Imen

In order to give better visibility on the answered topics, please click on 'Best answer' on the reply which solved your issue or answered your question. Thanks
Ramin1
Ramin1AuthorBest answer
Associate II
December 13, 2021

Hi @Imen DAHMEN​ ,

Thanks for getting back to me, it is now working and here is the conclusion:

SPI1 was derived of Port G on our board and I had to enable VDDIO2 via PWR

ST Technical Moderator
December 13, 2021

Hi @Ramin​ ,

Really glad to know you overcame this problem, and thank you for all the update you provided.

Imen

In order to give better visibility on the answered topics, please click on 'Best answer' on the reply which solved your issue or answered your question. Thanks