STM32U575RIT6Q flash memory interface question

[yyc]

Hello,

 

I am wondering what is the memory interface of the embedded 2MB flash? Like is it SPI .etc

 

Thank you!

[Andrew Neil]

There’s a block diagram in the Datasheet - it shows that the Flash on the AHB bus:

https://www.st.com/resource/en/datasheet/stm32u575ri.pdf#page=21

 

 

 

PS:

AHB is part of ARM’s Advanced Microcontroller Bus Architecture (AMBA):

https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture#Advanced_High-performance_Bus_(AHB)

https://www.arm.com/architecture/system-architectures/amba

[yyc]

Thank you very much! 

[AScha.3]

The internal flash memory interface of the STM32U575 achieves high-speed performance at up to 160 MHz by utilizing a 128-bit wide flash read bus paired with the updated ART Accelerator (Adaptive Real-Time Accelerator). [1, 2]

The Wide 128-Bit Read Line (Parallel Loading)

Instead of fetching data byte-by-byte, the internal flash interface reads from the memory array in wide parallel lines: [1, 2]

• Data Bus Width: Every single flash memory read operation automatically loads a 128-bit wide row from the flash bank. [1]
• Instruction Density: A single 128-bit read cycle simultaneously extracts four 32-bit instructions or eight 16-bit instructions into the prefetch/cache registers. [1]
• Hardware Prefetch: You can enable the prefetch engine via the PRFTEN bit in the Flash Access Control Register (FLASH_ACR). When enabled, the interface proactively fetches the next sequential 128-bit block while the CPU is executing the current one. This minimizes pipeline stalls during sequential code execution. [1, 2, 4]