Question
STM32U575: is it possible to disable blocking the read and write accesses to the backup registers, backup SRAM and SRAM2 when the tamper flag is set? To use tamper input for information and not security purpose.
According to RM: "In the NOERASE configuration (TAMPxNOER=1 in the TAMP_CR2 register, ITAMPxNOER=1 in the TAMP_CR3 register), the backup registers and other device secrets are not erased when the corresponding tamper event is detected. In addition, the read and write accesses to the backup registers and to other device secrets are blocked as soon as this potential tamper detection flag is set (tamp_potential signal, set if at least one TAMPxF or ITAMPxF is set), until this flag is cleared."