STM32U5 SYSCFG is RAZ/WI with TrustZone disabled

[adiroot]

While attempting to enable the divide by zero floating point interrupt, I ran into an issue with the U5:

• All SYSCFG registers are RAZ/WI even though TZEN is 0 and system is in privileged mode

Initially, a call was made to LL_SYSCFG_EnableIT_FPU_DZC to enable the floating point divide by zero interrupt. That does a read/modify/write of the SYSCFG->FPUIMR register.  When that had no effect, a deeper look was taken at accessing the SYSCFG register.

Setup:

• NUCLEO-U575ZI-Q hardware
  • Using built-in ST-Link and J-Link
  • Also reproduced on STM32U575I-EV via ST-Link
• STM32CubeMxIDE 1.11
• SYSCFG registers examined with STM IDE debugger SFRs window
  • All SYSCFG show as zero
  • Examined programmatically with the same results.
  • Memory browser window shows all zeroes as well
  • SYSCFG starts at address 0x46000400
  • Multiple checks were made, some on first instruction after boot, some later in the program during SystemInit()
  • Writing any non-zero value to SYSCFG->FPU_IE fails - the value stays at zero.
    • Writes attempted via SFRs window and programatically.
• Note that certain SYSCFG registers are not supposed to be zero at bootup
  • SYSCFG->FPSCR should read 0x1F at reboot according to ref. manual.
  • SYSCFG->CCCSR should read 0xA
  • They all show as zero
• TrustZone checked via SFRs and programatically
  • FLASH_OPTR->TZEN reads zero. FLASH_OPTR reads 0x1FEFF8AA.
• Privileged access checked via control register
  • Via IDE Registers view, General Registers, control, reads zero.
  • Programatically via __get_CONTROL() reads zero.

I have gone over the reference manual, errata, and other sources. I cannot find any information on what else is required to access SYSCFG.

Ultimately, the goal is to enable FPU divide by zero interrupt. A workaround to achieve that would suffice.

Thanks for your time and consideration.

[adiroot]

I found another way of enabling the floating point divide by zero interrupt! Via HAL

 HAL_NVIC_SetPriority(FPU_IRQn, 0, 0);
 HAL_NVIC_EnableIRQ(FPU_IRQn);

And the interrupt does happen after a divide by zero operation.

Clearly, the approach via LL_SYSCFG_EnableIT_FPU_DZC is either wrong or requires additional steps.

[Pavel A.]

How about __HAL_RCC_SYSCFG_CLK_ENABLE() ?

[adiroot]

A call to __HAL_RCC_SYSCFG_CLK_ENABLE() fixed it!

SYSCFG can be read after calling __HAL_RCC_SYSCFG_CLK_ENABLE()

Thank you for your help!