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Pratik Savle
Associate
Nov 1, 2026 6:09 AM UTC
Question

STM32N6570 XSPI1 HyperBus – Differential Clock (NCLK) Not Observed on PO5

 

Hello STMicroelectronics Support Team,

We are working on HyperRAM integration with the STM32N6570 using XSPI1 Port 1 in HyperBus mode.

Our hardware uses the following connections:

  • PO4 – XSPI1_CLK (CK)

  • PO5 – XSPI1_NCLK (CK#)

As per the STM32N6 hardware documentation, both CK and CK# are expected to be available for the differential clock interface.

However, during our hardware testing, we observe clock activity only on PO4 (CK). PO5 (NCLK) remains constantly HIGH, even while HyperRAM transactions are taking place.

Current XSPI configuration:

hxspi->Init.MemoryMode = HAL_XSPI_SINGLE_MEM;
hxspi->Init.MemoryType = HAL_XSPI_MEMTYPE_HYPERBUS;
hxspi->Init.MemorySize = HAL_XSPI_SIZE_512MB;
hxspi->Init.MemorySelect = HAL_XSPI_CSSEL_NCS1;
hxspi->Init.ChipSelectHighTimeCycle = 4;
hxspi->Init.FreeRunningClock = HAL_XSPI_FREERUNCLK_DISABLE;
hxspi->Init.ClockMode = HAL_XSPI_CLOCK_MODE_0;
hxspi->Init.WrapSize = HAL_XSPI_WRAP_NOT_SUPPORTED;
hxspi->Init.SampleShifting = HAL_XSPI_SAMPLE_SHIFT_NONE;

HyperBus configuration:

sHyperbusCfg.RWRecoveryTimeCycle = 4;
sHyperbusCfg.AccessTimeCycle = 6;
sHyperbusCfg.LatencyMode = HAL_XSPI_FIXED_LATENCY;

Register observations:

XSPI DCR1 = 0x04190300
XSPI DCR2 = 0x00000001
XSPI DCR3 = 0x00000000
XSPI CR   = 0x10000301
XSPIM CR  = 0x00000000

The HyperRAM device is detected successfully, and we can read its device ID (0x860F). Therefore, the basic HyperBus communication is operational.

We would appreciate your clarification on the following questions:

  1. Does STM32N6570 XSPI1 automatically generate the complementary NCLK signal when configured in HyperBus mode?

  2. Is there any additional XSPI or XSPIM register configuration required to enable differential clock output on PO4/PO5?

  3. Is there a specific HAL API or configuration parameter to enable differential clock operation?

  4. Does the XSPIM port configuration need to be enabled for NCLK generation, even when the default pin routing is used?

  5. Are there any known limitations or errata related to XSPI1 NCLK generation on STM32N6570?

Could you please share a reference configuration, HAL example, or register-level guidance for enabling CK/CK# output on XSPI1 Port 1?

We can provide our schematic, pin configuration, driver source code, and oscilloscope captures if required.

Best Regards,
Pratik

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