STM32N6570_DK not receiving data at CSI receiver

[priyankasalvi]

Hi Team,

 

We are trying to send camera feed through the TP2860 video decoder to STM32N6570_DK. We have confirmed the configuration of the TP2860 and receiving data at the TP2860 MIPI output, but not receiving packets at the STM32n6570 CSI end. We are positive the CSI configuration is done correctly, but please let us know if we are missing anything sharing the function and also attaching the log :

void stm32n6_mipi_host_enable(void)
{

    /* =========================================================================
     * STEP 1: FORCE MIPI CORE INTO SHUTDOWN / DISABLED STATE
     * =========================================================================
     * Clear PEN (Bit 1) in CSI_PRCR and clear power bits in CSI_PCR.
     * This releases the write-protection lock on the configuration registers.
     */
    CSI_PRCR &= ~(1 << 1);
    CSI_PCR  &= ~0x0000000F;
    k_msleep(5); // Wait for internal finite state machines to safely idle

    /* =========================================================================
     * STEP 2: CONFIGURE LANE MERGER (Static Configuration while CSIEN = 0)
     * =========================================================================
     * Configures: 2 valid data lanes, 1-to-1 physical-to-logical lane mapping.
     */
    CSI_LMCFGR = 0x00210200;
    k_msleep(5);

    /* =========================================================================
     * STEP 3: ENABLE CSI HOST CONTROLLER BASE
     * =========================================================================
     * Must be enabled AFTER lane merger, but BEFORE configuring Virtual Channels.
     */
    CSI_CR = (1 << CSI_CR_CSIEN_BIT);
    k_msleep(5);

    /* =========================================================================
     * STEP 4: CONFIGURE VIRTUAL CHANNEL (Strict Data Type Filtering)
     * =========================================================================
     * Configures VC0 for Individual Data Type mode (ALLDT = 0)
     * Enables Data Type 0 (DT0EN = 1)
     * Maps DT0 to MIPI Code 0x1E (Strictly YUV422 8-bit)
     * Sets DT0 Format to 8-bit words (DT0FT = 0x02 / BPP8)
     */
    CSI_VC0CFGR1 = 0x023E0002;
    k_msleep(5);

    /* =========================================================================
     * STEP 5: WATCHDOG CONFIGURATION
     * =========================================================================
     * Leaving CSI_WDR at 0x0 disables the watchdog feature for easier bring-up.
     */
    CSI_WDR = 0x00000000;

    /* =========================================================================
     * STEP 6: POWER ON PHYSICAL D-PHY LANES
     * =========================================================================
     * Power up physical layers: DL1EN=1, DL0EN=1, CLEN=1, PWRDOWN=0
     */
    CSI_PCR = 0x0000000E;
    k_msleep(5);

    /* Take physical D-PHY receiver core out of digital reset (PEN = 1) */
    CSI_PRCR |= (1 << 1);
    k_msleep(25); // Give clock recovery phase-locked loops (PLL) time to stabilize

    /* =========================================================================
     * STEP 7: KICKOFF DATA RECEPTION
     * =========================================================================
     * Fire the start pulse for Virtual Channel 0 while keeping CSIEN enabled.
     * Note: Because VC0START is a write-only pulse bit, we write directly
     * without using '|=' to avoid side effects.
     */
    CSI_CR = (1 << CSI_CR_VC0START_BIT) | (1 << CSI_CR_CSIEN_BIT);

    return 0;
}

 

 

[KDJEM.1]

Hello ​@priyankasalvi and welcome to the community;

 

Do you have the same issue when using the HAL drivers?

I recommend you to look at DCMIPP examples and Introduction to digital camera interface pixel pipeline for STM32 MCUs - Application note and check your configuration.

 

Thank you.

Kaouthar

[priyankasalvi]

Hello Kaouthar,

 

Thank you for replying, I have taken your opinion of confirming the DCMIPP configuration into consideration, but my issue is at the CSI PHY end, I am not seeing any signal here. That is why I need your help and expertise, specifically with some values like HSFR and CCFR as there is not much help in the datasheet regarding it, I will update you with our latest issue in detail.

We are currently facing an issue with the AHD-to-CSI interface on the CSI receiver side.

The primary issue is that the CSI PHY does not appear to be receiving any valid input. We are monitoring the CSI status registers, CSI_SR0 and CSI_SR1, to determine the PHY state.

The register values observed are as follows:

CSI_SR0

• CSI_SR0 = 0x00020000

CSI_SR1

• At startup: 0x74180000

• Majority of the time: 0x64100000

• Occasionally: 0x64180000

Based on these register values, our understanding is that the CSI PHY is not detecting the incoming clock.

To verify the hardware, we checked the CSI interface using an oscilloscope and confirmed that both the clock and data signals are present at the STM hardware pins. However, these signals are not reflected in the CSI status registers, and the PHY does not appear to recognize them.

For the CSI configuration, we have followed the datasheet recommendations. We have attached the relevant configuration screenshot for reference. We would appreciate it if someone from your team could review our CSI configuration and let us know if anything appears to be incorrect.

Additionally, we are sharing our main.c file and log file along with this email for your review.

Our expected CSI input configuration is:

• Clock: 300 MHz

• Data rate: 600 Mbps per lane

• Number of data lanes: 2

• Data format: YUV422, 8-bit

Could you please review our configuration and advise if there are any issues or additional checks that we should perform?

Thank you for your support.

Best regards,
Priyanka Salvi