STM32N657 IO drive strength

[kadam]

Hello Team,

We are using STM32N657 in our custom board design. We are operating MCU with 1.8V voltage level.

We are facing some challenges regarding drive strength issue. We have set “Very High Speed” in GPIOx_OSPEEDR register but not able to meet multiple peripherals rise time and fall time requirement. 

We are defining below resisters.

1. GPIOx_MODER : Alternate function mode
2. GPIOx_OTYPER : Output push-pull (reset state)
3. GPIOx_OSPEEDR : Very high speed
4. GPIOx_PUPDR : No pull-up, pull-down (00) & Pull-up (01) (Both values we have tried)

It would be helpful if you could guide us in resolving this issue and let us know if we have missed any register configuration or if any register values have been configured incorrectly.

Your quick response is much appriciated.

Thanks.

[RomainR.]

Hello ​@kadam 

When VDD and VDDIOx are powered at 1.8 V, you must enable the corresponding HSLV_VDD and HSLV_VDDIOx to switch the GPIOs in low voltage mode (1.8V range).

By default, the GPIOs on the N6 are 3.3 V tolerant. Therefore, it is necessary to program the OTP124 word and configure the PWR_SVMCRx registers by firmware, as explained in AN5967 - Rev 6, Section 12.4, “IO speed settings.”

Please also refer to Tr/Tf specification in DS14791 Table 69 and Table 70 with and without HSLV and IO speed.

See also the following useful resources:

• https://www.youtube.com/watch?v=lwSUNifpJso&t=480s
• https://community.st.com/stm32-mcus-60/how-to-program-the-otp-fuse-bits-in-the-stm32n6-148456?tid=148456&fid=60

Best regards,

Romain

[kadam]

Hello Romain,

Thank you for your response.

In our design, we are using VDD and VDDIO2-5 all at 1.8V level and turn on with below sequense

When 1.8V available, below domains are turn on.

1. VDD
2. VBAT
3. VDDA18AON
4. VDDIO4
5. VDDIO5
6. VDDA18PLL
7. PDR_ON

Once PWR_ON signal is available from STM32N657 MCU

1. VDDIO2
2. VDDIO3
3. VDDA18CSI
4. VDDA18USB
5. VDDA18ADC
6. VDDSMPS (using internal SMPS)
7. VDDA18PMU
8. VREF+

Below is schematic reference

While revieing reference from STM side regarding “How to program the OTP fuse bits in the STM32N6”

I found that there is particular sequence is mentioned as per below

So could you please guide us there any particular sequence do we need to follow because we are using all power domains at 1.8V.

Thanks

[RomainR.]

Hi ​@kadam 

Figure 2, "STM32N6 power-on sequence (two steps execution)" in AN5967, shows that it is possible to group some or all VDDIOx supplies together, or to make them independent of VDD. This in 3.3V or 1.8V.

This is your case, since VDDIO2/VDDIO3 are sequenced by PWR_ON, while VDD/VDDIO4 and VDDIO5 are powered up first.

When all supplies are configured at 1.8 V, this does not change anything. TheVDDIOxVSEL configuration sequence should be implemented in your firmware, at a very early stage (at the beginning of the FSBL), and before using any peripherals powered by VDDIO2 to VDDIO5 (external memories or SDMMC).
But, the OTP word 124 must be programmed one time first.

You can refer to the following example:
https://github.com/STMicroelectronics/STM32CubeN6/blob/main/Projects/STM32N6570-DK/Examples/XSPI/XSPI_PSRAM_MemoryMapped/FSBL/Src/stm32n6xx_hal_msp.c
https://github.com/STMicroelectronics/STM32CubeN6/blob/main/Projects/STM32N6570-DK/Examples/XSPI/XSPI_NOR_MemoryMapped_DTR/FSBL/Src/stm32n6xx_hal_msp.c
 

Best regards,

Romain,