STM32N6 DCMIPP CSI-2 D-PHY: does it support non-continuous (gated) clock? Clock lane never locks (ACTCLF=0) with a streaming sensor
Hardware: STM32N657 + DCMIPP CSI-2 Host (Synopsys DWC D-PHY). Sensor: onsemi AR0144CS, MIPI 2-lane, RAW12 (DT 0x2C), 27 MHz EXTCLK, link ≈
445 Mbps/lane, PHYBitrate = DCMIPP_CSI_PHY_BT_450.
Symptom - the receiver clock lane never enters HS:
- The sensor is definitely streaming: its FRAME_COUNT (0x303A) advances ~58 fps read over I2C; RESET_REGISTER = 0x005C (STREAM=1).
- The CSI host decodes exactly one Frame-Start short packet, then nothing — csi_sof=1, csi_eof=0, framebuffer stays black, and all error
counters are zero (ECC=0, CRC=0, SYNC=0, no SoT errors).
- CSI_SR1 = 0x64100000 → ACTCLF (bit31) = 0 (RM0486 §40.9: ACTCLF = D-PHY_RX RxClkActiveHS). STOPCLF (bit28) = 0. So the clock lane never
reaches sustained HS.
Key control comparison (same board, same DCMIPP/CSI receiver): a Sony IMX708 in continuous-clock mode reaches ACTCLF=1 ("CDR locked") in ~1
ms and captures full frames. Only the AR0144 (which I believe emits a non-continuous/gated clock) fails — ACTCLF stays 0.
What I've already tried (no change to ACTCLF):
- Correct HSFR/bitrate for ~445 Mbps (BT_450); verified osc_freq_target programmed.
- Swept osc_freq_target 460 → 600 → 900 (longer T_HS_SETTLE).
- Raised sensor FRAME/LINE preamble.
- Re-ordered bring-up so the sensor streams (lanes at LP-11) before arming the receiver, and re-ran HAL_DCMIPP_CSI_SetConfig against the
live lanes.
- Set FRXMDL0/1 (force data-lane RX) in CSI_PMCR.
Questions:
1. Does the STM32N6 CSI-2 Host / DWC D-PHY support reception of a non-continuous (gated) MIPI clock (clock lane dropping to LP-11 during
blanking, requiring per-burst LP→HS re-acquisition)?
2. If yes — which register/bit or HAL field enables it (e.g., a CSI_PMCR bit, a D-PHY test-register write via CSI_PTCR0/1, or a
DCMIPP_CSI_ConfTypeDef option)? I see no such control in DCMIPP_CSI_ConfTypeDef (only NumberOfLanes, DataLaneMapping, PHYBitrate).
3. If no — please confirm the STM32N6 CSI requires a continuous clock, so I can document the constraint.
