stm32L4S5, spi pause between 8-bit frames

[heisenbug]

Hi all,

i am performing some 400bytes blocks transferts by SPI, at 16Mhz.

I have NSS off, so no CS up/down between frames.

From some testing, whatever system clock i set, or whatever spi clock i set, there is a fixed 4us time between 2 consecutive frames. This pause is of course very visible and heavy at 20Mhz spi clock, by scope something like:

__||||||||_____________||||||||______________|||||||_____

Transfer is done by LL_SPI_TransmitData8

If any help to reduce this delay between frames, would be very good, or at least to know i cannot reduce it in any way will be helpful too.

thanks a lot

 

 

[heisenbug]

@waclawek.jan thanks will go better through  your comments. I am in the bounds of Zephyr driver, no much freedom.

No, i am not on QSPI.

[waclawek.jan]

> I am in the bounds of Zephyr driver, no much freedom.

And I am willing to bet, that that's where the delays come from.

JW

[heisenbug]

@waclawek.jan 

well, dma clocks are all disabled,

also, i tried already to write constant values, there is not benefit.

also, if it was a code overhead issue, increasing 30% the clock i should have see some benefit, while not happening.

Anyway, i could have an additional improvement, in Zephyr there is a "fifo enabled" setting that for some reason was not set. Enabling it (not just hardcoded a 1), so using fifo, gap goes from 1.8us to 0.9us.

Quite good for my case.

[heisenbug]

no, looks like i cannot enable that "fifo-enable", i am getting some errors, it's a special fifo for st_stm32h7_spi

[AScha.3]

I am surprised - because i think, fifo cannot be "disabled" , its inseparable part of the spi unit.

 

[heisenbug]

Hi,

i finally found out that delay between frames is due to the "transmit()" function os overhead, as @TDK  correctly said in his first reply (i did this test initially moving mcu clock from 80 to 120Mhz, but probably i was not switching to 120Mhz at all).

 

- testing SPI without any os (bare metal, direct reg write), at 80Mhz mcu clock, i can reach about 10Mbit/s on a 20Mhz spi clock (there is still about 1 frame delay between 2 frames but it's ok for me).

- on zephyr os, with spi interrupts disabled, with speed optimizations (-O2), and speeding up mcu clock from 80 to 120Mhz my inter-frame time is 860ns, this is the best i can do now with this os (5Mbit/s), but this is also due to the fact that SPI clock (set to 25Mhz) is auto-setting down to 15Mhz, not clear why. If i could increase this SPI clock, i should be able to get near 10Mbit. Is there any way ?

 

Thanks