STM32L4P5 ocotspi issues

[zeboss49]

Hello,

I have two issues with the octospi controllers of the STM32L4P5.

First issue.

I can’t get both controller to work simultaneously.

My target was to use one controller with a QSPI flash (W25Q512JVEIQ) and the second one with an APMemory QSPI PSRAM (APS6404L).
I started the project by getting the code to work (it was a port from an STM32L496 project) for the flash.

After some adjustments, the code works properly in quad spi mode.

Then I added the second controller and doing that brokes the project.

The second controller works, but the first one stopped working.

I run some checks with a logic analyzer and found that ther is no signals on the I/O lines.

CS# is HIGH and never goes low and there is no clock.

CS# and clock are properly generated for the second controller.

Second issue

I can’t get the memory mapped mode to work.

The mode is p^roperly enabled, I can read data from 0x90000000 without throwing a hard fault, but data is always 0.

I’m wondering if this could be related to the flash model.

It does not support QPI mode.

Is QPI mode required for memeory mapped  mode to work ?

Here after is my code to enable memory mapped mode:

static void w25qxxx_Enable_memory_mapped(void)
{
	OSPI_MemoryMappedTypeDef	_cfg = {0};
	OSPI_RegularCmdTypeDef		_ospi_rd_command = {0};
	OSPI_RegularCmdTypeDef		_ospi_wr_command = {0};
	HAL_StatusTypeDef			_hal_status;

	_cfg.TimeOutActivation = HAL_OSPI_TIMEOUT_COUNTER_DISABLE;

	_ospi_rd_command.OperationType = HAL_OSPI_OPTYPE_READ_CFG;
	_ospi_rd_command.FlashId = HAL_OSPI_FLASH_ID_1;
	_ospi_rd_command.NbData = 1;

	if (system_hardware_config->flash_read_mode == FLASH_RW_MODE_QUAD)
	{
		_ospi_rd_command.Instruction = W25Q_FAST_READ_QUAD_OUT_4B;
		_ospi_rd_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
		_ospi_rd_command.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
		_ospi_rd_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
		_ospi_rd_command.DataMode = HAL_OSPI_DATA_4_LINES;
		_ospi_rd_command.DummyCycles = 8;
	}
	else if (system_hardware_config->flash_read_mode == FLASH_RW_MODE_DUAL_SINGLE)
	{
		_ospi_rd_command.Instruction = W25Q_FAST_READ_DUAL_OUT_4B;	 	// COMMAND
		_ospi_rd_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
		_ospi_rd_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
		_ospi_rd_command.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
		_ospi_rd_command.DataMode = HAL_OSPI_DATA_2_LINES;
		_ospi_rd_command.DummyCycles = 8;
	}
	else
	{
		_ospi_rd_command.Instruction = W25Q_FAST_READ_4B;	 	// COMMAND
		_ospi_rd_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
		_ospi_rd_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
		_ospi_rd_command.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
		_ospi_rd_command.DataMode = HAL_OSPI_DATA_1_LINE;
		_ospi_rd_command.DummyCycles = 8;
	}
	_ospi_wr_command.OperationType = HAL_OSPI_OPTYPE_WRITE_CFG;
	_ospi_wr_command.FlashId = HAL_OSPI_FLASH_ID_1;
	_ospi_wr_command.NbData = 1;

	if (system_hardware_config->flash_read_mode == FLASH_RW_MODE_QUAD)
	{
		_ospi_wr_command.Instruction = W25Q_PAGE_PROGRAM_QUAD_INP_4B;	 	// COMMAND
		_ospi_wr_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
		_ospi_wr_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
		_ospi_wr_command.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
		_ospi_wr_command.DataMode = HAL_OSPI_DATA_4_LINES;
	}
	else
	{
		_ospi_wr_command.Instruction = W25Q_PAGE_PROGRAM_4B;	 	// COMMAND
		_ospi_wr_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
		_ospi_wr_command.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
		_ospi_wr_command.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
		_ospi_wr_command.DataMode = HAL_OSPI_DATA_1_LINE;
	}
	_hal_status = HAL_OSPI_Command(&hospi1, &_ospi_rd_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
	if (_hal_status != HAL_OK)
	{
		_hal_status = HAL_OSPI_GetError(&hospi1);
		HAL_OSPI_Abort(&hospi1);
	}
	else
	{
		_hal_status = HAL_OSPI_Command(&hospi1, &_ospi_wr_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
		if (_hal_status != HAL_OK)
		{
			_hal_status = HAL_OSPI_GetError(&hospi1);
			HAL_OSPI_Abort(&hospi1);
		}
		else
		{
			_hal_status = HAL_OSPI_MemoryMapped(&hospi1, &_cfg);
			if (_hal_status != HAL_OK)
			{
				_hal_status = HAL_OSPI_GetError(&hospi1);
				HAL_OSPI_Abort(&hospi1);
			}
		}
	}
}

The code was teste in QUAD configuration (FLASH_RW_MODE_QUAD)

Thanks in advance for your help.

 

[KDJEM.1]

Hello ​@zeboss49 ;

 

Are you using STM32CubeMx to generate project?

If yes, Please look at  OCTOSPI: HAL_OSPIM_Config() | Community.

For the second issue, I recommend you to look a AN5050 precisely Table 7. STM32CubeMX - Configuration of OCTOSPI signals and mode and III. Quad-SPI PSRAM in Regular-command protocol example section. This may help you to configure the OCTOSPI1 in Indirect/Memory-mapped mode and to configure the external Quad-SPI PSRAM AP Memory allowing communication in STR Quad-SPI mode.

 

Thank you.

KAouthar

[zeboss49]

Hello,

I’m using CubeMX to generate the project.

I’ll look at the refferenced topic.

For the second point, your answer lacks an important information about the QUAD SPI mode, are you speaking of the regular QUAD SPI mode or the QPI mode?

The exemple tells nothing about it as the APMemory chip only supports QPI mode.

The main differences between regular QUAD SPI mode and QPImode is that in QPImode all the transfers, including the command, is done using four lines.

If QPI compliant chip is required, I can switch to a GD25B512ME flash chip which is QPI and DTR compliant.

[KDJEM.1]

Hello ​@zeboss49 ,

 

Glad to know that the first issue is solved.

Is the DQS enabled? Please look at STM32L4P5xx/Q5xx device errata - Errata sheet for OCTOSPI limitations.

 

Thank you.

Kaouthar

[zeboss49]

Hello,

DQS is enabled in OCTOSPIM, but is not in the OCTOSPI instances.
I did’n’t put the modified code in octospi.c, I rather paste it at the beginning of the main task, avoiding the boring process to have to modify octospi.c each time I re-run CubeMX.

Didier

[zeboss49]

Hello,

I’ve conducted some test with both OCTOSPI controllers working simultaneously.

Usiong the same code to activate the memory maped mode (at the except of the hospi item) it appears that ùeùory mapped mode works like a charm with the APMemory APS6404L 8MB QUAD SPI PSRAM CHIP and does niot work with the W25Q512JVEIQ chip.

From my point of view, the answer to the second point is that a QPI compliant chip is required for memory mapped mode to work.

I don’t see any obvious reason to this, the read config and write config do provide information whatever the mode is and it should work.

Regards

Didier

[zeboss49]

Hello,

to close the post.

I ran tests with a W25Q128JVPIM DTR.

This chip does support QPI mode and it appears that memory mapped mode is working with it.

To conclude, using memory mapped mode does require a QPI compliant chip.

Regards

Didier